Fig. 2.10 Interrupt-Processing Flowchart - Fujitsu MB89140 Series Hardware Manual

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INTERRUPT

CONTROLLER

HARDWARE CONFIGURATION

Description of Operation

The functions of interrupt controllers are described below.

Interrupt functions

The MB89140 series of microcontrollers have 12 inputs for interrupt re-

quests from each resource. The interrupt level is set by 2-bit registers corre-

sponding to each input. When an interrupt is requested from a resource, the

interrupt controller receives it and transfers the contents of the correspond-

ing level register to the CPU. The interrupt to the device is processed as

follows:

(a)An interrupt source is generated inside each resource.

(b)If an interrupt is enabled, an interrupt request is output from each re-

source to the interrupt controller by referring to the interrupt-enable bit

inside each resource.

the priority of simultaneously-requested interrupts and then transfers the

interrupt level for the applicable interrupt to the CPU.

(d)The CPU compares the interrupt level requested from the interrupt con-

troller with the IL bit in the processor status register.

(e)As a result of the comparison, if the priority of the interrupt level is higher

than that of the current interrupt processing level, the contents of the I-

flag in the same processor status register are checked.

(f) As a result of the check in step (e), if the I-flag is enabled for an interrupt,

the contents of the IL bit are set to the required level. As soon as the cur-

rently-executing instruction is terminated, the CPU performs the interrupt

processing and transfers control to the interrupt-processing routine.

(g)When an interrupt source is cleared by software in the user's interrupt

processing routine, the CPU terminates the interrupt processing.

Figure 2.10 outlines the interrupt operation for the MB89140 series of micro-

controllers.

Internal bus

MB89140 CPU

Enable FF

Source FF

(g)