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CVERALL TIMING RELATIONSHIPS
Earlier, wnen we discussed core stor-
age, we emphasized the fact that it is
an independent unit.
It communicates
with the CPT} through the memory-to-CPU
interface.
Core storage has its own
clock that is started by a signal from
the CPU.
This means that ROS requests
core storage service on one time
~sis
(CPU clock), whereas core storage
answers this request on another time
basis (memory clock).
Although these
two clocks operate independently, their
timings are definitely related.
When
the ROS reC'ds out a word that .requests
core storage service, the mem.ory clock
is signalled to start at the beginning
of the next CPU cycle.
In Figure 3-58
read call is
develoF~d
and sent to the
core storage unit as a result of the
statem.ent IJ->MN.
Read call starts the
3-80
memory dock and specifies a memory read
cycle.
While the core storage unit ls
reading out the requested byte, the Res
is reading out and executing the second
micro-word.
When the memory has the
requested byte ready (about T4 time), it
signals the CPU with the data ready
signal.
The CPU then accepts the byte
and gates the byte to the R-register.
The second micro-word contained the
statement write.
Thus when the core
stora~e
unitfinishes its read cycle,
the write statement develops the write
call signal to start the memory clock
tor a memory write cycle.
These timing
relationships are important because they
point out how the core storage cycle
seems to be one cycle behind the CPU
cycle.
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