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ADDRESS 03A4:
The second byte of data
from both registers is added and the
result is stored in the R-register
(R:!:D+C->RC) •
The result of this second addition is
000000000.
S2 is not
~et
to a zero
(ANSNZ->S2) even though there is nothing
on the Z bus because theS-register is
not made up of polarity hold latches.
It takes a definite reset expression to
clear an S-register position to Zero
(O->SO) •
S6 and S5 are again tested to
determine the branch set up.
Neither
position has been set to one therefore
the 0, 0 branch is again taken to
address 01DO.
R->W sets the W-register
of ROAR to the value of one because of
the high-order address change.
ADDRESS 0100:
The second byte of data
is regenerated (WRITE).
A 1,0 branch is
taken to address OlCE.
ADDRESS 01CE:
Byte 1 of general pur-
pose register 5 is addressed (UV->MN
MILS).
The address for byte 1 of reg-
ister 7 is set up (T-O->T).
S5 is still not set to a one because
the data on the Z bus is
Reg 7
Byte 1.
0111
0001
Take the 0,1 branch to 01C1
ADDRESS 01Cl:
Byte
1
from register 5
is stored in the D-register (R->D).
It
is also regenerated (WRITE).
R->W is
again used for our address change.
Take
the 1,1 branch to address 03A3.
ADDRESS 03A3:
Byte
1
from register 7 is
read (T->N LS).
The address for general
purpose register 5, byte 0 is obtained
(V-O->V).
Branch 0,0 to address 03A4
because S7 is still zero.
ADDRESS 03A4:
Add byte-l data from
both registers (R:!:D+C->RC).
S2 is still
set to 1 and cannot be changed by the
.expression ANSNZ->S2.
S6 and S5 are
still zero.
Branch to Address 0100.
ADDRESS 0100:
Regenerate (WRITE) the
sum to core.
Branch 1,0 to
address
OleE.
ADDRESS 01CE:
Read the last byte of
data from register 5 (UV->MN M/LS).
Change the address in the T-register
(T-O->T) •
Reg 7
Byte 1
Old T-register address
= 0111
0001
minus 0
=
1111
1111
Reg 7
Byte 0
New T-register address
=
0111
0000
The information on the Z bus as a
result of the arithmetic statement is
0111 0000.
The low-order four bits are
0000.
The C line of the box has the
expression LZ->S5.
S5 is now set to a 1
because the low position of the Z bus is
zero (LZ).
Advance to address 01Cl.
ADDRESS 01Cl:
Store the last byte of
data that came from register 5 (R->D).
Regenerate this data (WRITE).
Control
the address change
~->W).
Again check
G3, set up a 1,1 branch to address 03A3.
ADDRESS 03A3:
Address core and read
the last byte of data from register
7 (T->N LS).
Subtract one from the data
in the V-register.
This address,
0101
11", is invalid for register 5 but it
will not be used as we are in this loop
for the last time.
Check S7, which is
still zero, and branch 0,0 to
address 03A4.
ADDRESS 03A4:
Add the last byte of data
from both registers and store the result
in the R-register (R±D+C->RC).
S2 is still set and cannot be changed
by the expression ANSNZ->S2.
K->W sets
up an address change.
Positions 6 and 5
of the S-register are tested.
S5 had
been set to a
1,
therefore, a 0, 1
branch is taken to address 01Dl.
ADDRESS 0101:
The last byte is stored
in core
~RITE).
Register 7 now con-
tains our answer: 000000000 000000000
000000000 11110110.
The data in the R-
register for our last sum is 000000000.
In the expression R • K8->Z, this data
in the R-register is ANDed
(e)
with the
R source high
(H)
and gated_to the
Z
bus.
The value of R on the E line is
shown to be eight (1000).
3-33
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