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system.
This is explained in more
detail under Machine Check Handling.
ALLOW READ, ALLOW WRITE
Earlier, when we discussed the MN-
register, we discussed the importance of
not changing the MN-register between
read and write cycles.
A latch in the
CPU provides the necessary interlock to
prevent changing the MN-register and to
prevent taking succes.si ve memory read
cycles with no intervening write cycles.
The allow write latch is turned on with
a CPU read cycle and turned off with a
CPU write cycle to provide this
interlock.
The output of this allow
write latch controls the set of the
MN-register as well as the read call and
write call signals that define core
storage cycles.
R-REGISTER
The R-register acts as a single-byte
buffer for the transfer of information
between core storage and the CPU.
It is
both the source and data register for
2-64
the core storage unit.
Information to
be placed into the core storage unit
must first be gated through the ALU to
the R-register.
Once in the R-register,
this byte is available to the core stor-
age inhibit drivers via the memory/CPU
interface.
Likewise, information read
out of storage to be used by the CPU
must first be gated to the R-register.
From theR-register the information can
be gated to one of a number of registers
via the A-bus and the B-bus.
There are two levels of control for
placing data into the R-register.
First, the desired R-registe.r source is
selected and gated to the R-register
polarity hold latch data inputs.
This
source can be either Z-bus data (CPU) or
storage data (core storage).
The second
control is the R-register polarity hold
latch control line.
It is here that the
R-register set timing is determined.
If
the data source is core storage, the
R-register is set by data ready pulse
from core storage.
This occurs at
approximately T4-time.
If
the R-
register source is the Z-bus, the R-
register is set with the T4 pulse.
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