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Address selection above 8K is provid-
ed by the M-register 2- and l-hit posi-
tions.
These two bit positions allow
unique selection of one of the four 8K
blocks.
Absence of both M- register 2-
and l-bits indicates an address in the
range of 0000-8191, and therefore sel-
ects the basic 8K block.
An M-register
2-bit with no M-register l-bit specifies
an address in the range of 8192-16383.
This selects the second 8K block.
The
third 8K block has the address range of
16384-24575, and is selected by an M-
register l-bit with no M-register 2-bit.
If the address contains both M-register
2- and 1- bits, the fourth 8K block with
the addresses 24576-32767 is selected.
The drivers are controlled by the M-
register 2- and 1-bits and the read or
write signal.
32K AUXILIARY STORAGE
•
Either four or eight 256-byte
auxiliary storage areas included in
a 32K storage unit.
•
M-register 1-, 2-, and 3-bits deter-
1I1ine the auxiliary storage area to
be addressed.
•
•
N-register determines the specific
address from 00-255 within the aux-
iliary storage area defined.
CPU local storage is always the
high-order 256-byte auxiliary stor-
age area.
Standard auxiliary storage for a 32K
storage unit is four 256-byte areas (MPX
0, MPX 1, MPX 2, and CPU local storage).
These four areas are located in the
first 16K of storage, and are addressed
as described under 16K Auxiliary
Storage.
A special feature is available
that provides four additional 256-byte
blocks of auxiliary storage.
These
additional blocks of auxiliary storage
provide additional subchannels for the
iBultiplexor channel.
With the four additional blocks,
auxiliary storage is composed of eight
2-52
256-byte blocks of auxiliary storage
named MPX 0, MPX 1, MPX 2, MPX 3, MPX 4,
MPX 5, MPX 6, and CPU local storage.
When the CPU wishes to address a speci-
fic byte-location in one of these blocks
of auxiliary storage, the main-auxiliary
latch in the CPU is set to auxiliary,
and the desired byte-address is placed
into the N-register.
The CPU further
specifies which block of auxiliary stor-
age is to be addressed by coding the
M-registeD 1-,
2-,
and 3-bits as
follows:
M-reg
1-bit
M-reg
M-reg
Auxiliary Storage
2-bit
3-bit
J\rea Selected
0
0
0
MPX
0
0
0
1
MPX 1
0
1
0
MPX 2
0
1
1
MPX 3
1
0
0
MPX
4
1
0
1
MPX
5
1
1
0
MPX 6
1
1
1
CPU Local
CLeeK CONTROL ADDRESSING (64K)
•
64K core-storage unit composed of
two separate 32K core storage units.
•
Each 32K unit completely independent
of the other.
•
O-bit poSition of M-register deter-
mines which storage clock is started
Each 32K core-storage unit is a complete
package that cannot be be further
expanded by merely adding more planes to
the existing array.
The package
includes the core planes, the addressing
Circuitry, and the storage clock for
32,768 positions of core storage.
To
expand core-storage capacity requires
the addition of a similar 32K unit,
complete with core planes, addreSSing
circuitry, and storage clock.
In addi-
tion, the CPU provides a second MN-
register for second 32K storage unit
(Figure 2-59).
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