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Clock Start
lO I
A
Mach Reset
- - FL1·-
~
~~
r----""1-...I.---1
Delay Tap
--FL2--
From Line
Clock Sequence
1.
Machine reset turns FLl off, FL3 off.
2. FL
1
going off turns FL2 on.
3. Clock start turns on FL
1.
4. FLl and FL2 AND to impulsedelay line. Leading
edge of pulse propagates down de lay line.
5. Depending on pulse width desired, a delay line
output tap turns FL2 off.
6. Drive pulse to delay line falls; trailing edge of
pulse propagates down delay line.
7. FL2 going off turns FL 1 off, FL 1 going off turns
FL2 back on.
8, Leading edge of pulse from bottom tap of TD3 sets FL3.
9. Leading edge of drive pulse from FL3 propagates down
remainder of delay line.
10.
Depending on drive pulse width requirements, a
delay line tap turns FL3 off.
11.
Trailing edge of drive pulse propagates down TD4,
lO5, lO6.
Figure 2-54.
Delay Line Clock Drive
The storage clock consists of a ser-
ies of delay lines, delay line control
latches, and read and write clocking
pulse latches.
The control latches
develop the timing of and control the
width of the pulse that drives the delay
2-44
lO2
500 ns
lO3
750
ns
OR
Ma~c:!h~R:;ese~t~...r-'-
- FL3 - -
Delay Tap
TO 4
1000
ns
lO5
1250
ns
TD6
L--_ _ _ ---I~-
1500
ns
line.
The delay line consists of six
separate delay lines connected in
series.
Each delay line has ten
outputs.
There is a 25 nanosecond delay
between each of the ten outputs for a
total delay of 250 nanoseconds per delay
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