Resistor Schematic For Primary Ide Connectors; Resistor Schematic For Secondary Ide Connectors - Intel 810A3 Design Manual

Layout and Routing Guidelines
Figure 4-17. Resistor Schematic for Primary IDE Connectors
Figure 4-18. Resistor Schematic for Secondary IDE Connectors
4-14
P C I R S T _ B U F # *
PDD[15:8]
P D D [ 7 ]
PDD[6:0]
PDA[2:0]
P D C S 1 #
P D C S 3 #
P D I O R #
P D I O W #
P D D R E Q
5 V
1 k 8.2k
o h m o h m
P I O R D Y
I R Q 1 4
P D D A C K #
I C H
*Due to high loading, PCIRST# must be buffered.
P C I R S T _ B U F # *
SDD[15:8]
SDD[7]
SDD[6:0]
SDA[2:0]
S D C S 1 #
S D C S 3 #
S D I O R #
S D I O W #
S D D R E Q
5 V
1 k 8.2k
o h m o h m
S I O R D Y
I R Q 1 5
S D D A C K #
I C H
*Due to high loading, PCIRST# must be buffered.
22 - 47 ohm
5 V
1 0 k
5.6k
o h m
o h m
4 7 0 o h m
22 - 47 ohm
5 V
1 0 k
o h m
5.6k
o h m
4 7 0 o h m
Intel
R e s e t #
C S E L
Pin32
N.C.
R e s e t #
C S E L
Pin32
N.C.
®
810A3 Chipset Design Guide