Display Cache Checklist; Lpc Super I/O Checklist; Ide Checklist - Intel 810A3 Design Manual

Chipset platform
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Table 8-15. Display Cache Checklist
Checklist Line Items
CKE
Table 8-16. LPC Super I/O Checklist
Checklist Line Items
LPC_PME#
LPC_SMI#
LFRAME#
LAD[0:3]
LDREQ[0]#
Table 8-17. IDE Checklist
Checklist Line Items
CBLID#/PDIAG# (cable detect):
PDD[15:0], PDIOW#, PDIOR#,
PDREQ, PDDACK#, PIORDY,
PDA[2:0], PDCS1#, PDCS3#,
SDD[15:0], SDIOW#, SDIOR#,
SDREQ, SDDACK#, SIORDY,
SDA[2:0], SDCS1#, SDCS3#,
IRQ14, IRQ15
IDE Reset
PDD[15:0], SDD[15:0]
PIORDY, SDIORDY
IRQ14, IRQ15
PDDREQ, SDDREQ
CSEL
IDEACTP#, IDEACTS#
IOCS16#
®
Intel
810A3 Chipset Design Guide
4.7 KΩ pull-up resistor to VCC3.
Do not connect LPC PME# to PCI PME#.
If the design requires the Super I/O to support wake from any suspend state, connect
Super I/O LPC_PME# to a resume well GPI on the ICH.
This signal can be connected to any ICH GPI. The GPI_ROUTE register provides the
ability to generate an SMI# from a GPI assertion.
This signal is actively driven by ICH and does not require a pullup resistor.
No additional pull-up resistors required. These signals have integrated pullups in the
ICH.
This signal is actively driven by the Super I/O and does not require a pullup resistor.
Refer to the latest design guide for the correct circuit.
NOTE: All ATA66 drives will have the capability to detect cables.
No external series termination resistors required on those signals with
integrated series resistors.
This signal requires a 22–47 ohm series termination resistor and should
be connected to buffered PCIRST#.
PDD7 and SDD7 need a 10 KΩ (approximate) pull-down resistor to
ground.
Refer to ATA ATAPI-4 specification.
Need 1 KΩ (approximate) pull-up resistor to 5V.
Need 8.2 KΩ to 10 KΩ pull-up resistor to 5V.
Need 5.6 KΩ (approximate) pull-down resistor to ground.
Need 470 Ω (approximate) pull-down resistor to ground.
Can use a 10 KΩ (approximate) pull-up resistor to 5V for HD LED
implementation.
Leave as No Connect.
Design Checklist
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