Routing Di Sample Clock To An Output Terminal; Digital Waveform Generation; Do Sample Clock Signal - National Instruments NI 6221 User Manual

Digital Waveform Generation

DO Sample Clock Signal

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• PXI_STAR
• Analog Comparison Event (an analog trigger)
You can sample data on the rising or falling edge of di/SampleClock.

Routing DI Sample Clock to an Output Terminal

You can route di/SampleClock out to any PFI terminal. The PFI circuitry
inverts the polarity of di/SampleClock before driving the PFI terminal.
You can generate digital waveforms on the Port 0 DIO lines. The DO
waveform generation FIFO stores the digital samples. M Series devices
have a DMA controller dedicated to moving data from the system memory
to the DO waveform generation FIFO. The DAQ device moves samples
from the FIFO to the DIO terminals on each rising or falling edge of a clock
signal, do/SampleClock. You can configure each DIO signal to be an input,
a static output, or a digital waveform generation output.
The FIFO supports a retransmit mode. In the retransmit mode, after all the
samples in the FIFO have been clocked out, the FIFO begins outputting all
of the samples again in the same order. For example, if the FIFO contains
five samples, the pattern generated consists of sample #1, #2, #3, #4, #5,
#1, #2, #3, #4, #5, #1, and so on.
Use the DO Sample Clock (do/SampleClock) signal to update the DO
terminals with the next sample from the DO waveform generation FIFO.
M Series devices do not have the ability to divide down a timebase to
produce an internal DO Sample Clock for digital waveform generation.
Therefore, you must route an external signal or one of many internal signals
from another subsystem to be the DO Sample Clock. For example, you can
correlate digital and analog samples in time by sharing your AI Sample
Clock or AO Sample Clock as the source of your DO Sample Clock. To
generate digital data independent of an AI, AO, or DI operation, you can
configure a counter to generate the desired DO Sample Clock or use an
external signal as the source of the clock.
If the DAQ device receives a do/SampleClock when the FIFO is empty,
the DAQ device reports an underflow error to the host software.
6-5
Chapter 6 Digital I/O
M Series User Manual