Ethernet Phy Reset - Xilinx ZCU106 User Manual

Table 3-14: DP83867 PHY Connections to XCZU7EV MPSoC (Cont'd)
XCZU7EV
(U1) Pin
K29
K30
K31
K32
K33
K34
L29
L30
L33
L34

Ethernet PHY Reset

The DP83867IRPAP PHY U98 reset circuit is shown in
reset by the SW9 pushbutton (U59.6), the MAX16025 U22 MPSoC PS-side POR reset device
(U59.1), or the I2C0 connected U97 TCA6416A I/O expander port P06 pin 10 (U59.3).
X-Ref Target - Figure 3-13
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
Net Name
MIO68_ENET_TX_D3
MIO69_ENET_TX_CTRL
MIO70_ENET_RX_CLK
MIO71_ENET_RX_D0
MIO72_ENET_RX_D1
MIO73_ENET_RX_D2
MIO74_ENET_RX_D3
MIO75_ENET_RX_CTRL
MIO76_ENET_MDC
MIO77_ENET_MDIO
Figure 3-13: Ethernet PHY Reset Circuit
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Chapter 3: Board Component Descriptions
DP83867 PHY U98
Pin #
35
52
43
44
45
46
47
53
20
21
Figure 3-13. The DP83867IRPAP can be
Send Feedback
Pin Name
TX_D3
TX_EN_TX_CTRL
RX_CLK
RX_DO
RX_D1
RX_D2
RX_D3
RX_DV_RX_CTRL
MDC
MDIO
X19174-052417
55