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Chapter 1: ML501 Evaluation Platform
Note:
and Mode DIP Switches."
The board also features a System ACE failsafe mode. In this mode, if the System ACE
controller detects a failed configuration attempt, it automatically reboots back to a
predefined configuration image. The failsafe mode is enabled by inserting two jumpers
across J18 and J19 (in horizontal or vertical orientation).
The System ACE MPU port is connected to the FPGA. This connection allows the FPGA to
use the System ACE controller to reconfigure the system or access the CompactFlash card
as a generic FAT file system. The data bus for the System ACE MPU port is shared with the
USB controller.
18. ZBT Synchronous SRAM
The ZBT synchronous SRAM (ISSI IS61NLP25636A-200TQL) provides high-speed, low-
latency external memory to the FPGA. The memory is organized as 256K x 36 bits. This
organization provides for a 32-bit data bus with support for four parity bits.
Note:
19. Linear Flash Chips
A NOR linear flash device (Intel JS28F256P30T95) is installed on the board to provide
32 MB of flash memory. This memory provides non-volatile storage of data, software, or
bitstreams. The flash chip is 16 bits wide and shares its data bus with SRAM. The flash
memory can also be used to program the FPGA.
Note:
is designed to be asserted at power-on or at system reset.
20. Xilinx XC95144XL CPLD
A Xilinx XC95144XL CPLD provides general-purpose glue logic for the board. The CPLD
is located under the removable LCD and is not visible in
programmed from the main JTAG chain of the board. The CPLD is mainly used to
implement level translators, simple gates, and buffers.
21. 10/100/1000 Tri-Speed Ethernet PHY
The ML501 Evaluation Platform contains a Marvell Alaska PHY device (88E1111)
operating at 10/100/1000 Mb/s. The board supports MII, GMII, and RGMII interface
modes with the FPGA. The PHY is connected to a Halo HFJ11-1G01E RJ-45 connector with
built-in magnetics. The PHY is configured to default at power-on or reset to the following
28
System ACE configuration is enabled by way of a DIP switch. See
Caution!
Use caution when inserting a CompactFlash card with exposed metallic surfaces.
Improper insertion can cause a short with the traces or components on the board.
The SRAM and FLASH memory share the same data bus.
The reset for the AC97 Codec is shared with the reset signal for the flash memory chips and
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"31. Configuration Address
Figure
1-2. The CPLD is
ML501 Evaluation Platform
UG226 (v1.3) November 10, 2008
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