Intel Arria 10 series User Manual page 25

2 Intel FPGA HDMI Design Example Detailed Description
UG-20077 | 2017.11.06
Clock
TX/RX Video Clock
RX TMDS Clock
RX CDR Reference Clock
RX Transceiver Clock Out
Management Clock
Signal Name in Design
vid_clk
tmds_clk_in
iopll_outclk0
rx_clk
mgmt_clk
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Intel FPGA HDMI Design Example User Guide for Intel
Description
TMDS Bit Clock Ratio Link Speed Clock Frequency
0 TMDS clock frequency/ Symbol
per clock
1 TMDS clock frequency *4 /
Symbol per clock
Video data clock. The video data clock frequency is derived
from the TX link speed clock based on the color depth.
TMDS Bit Clock Ratio Video Data Clock Frequency
0 TMDS clock/ Symbol per clock/
Color depth factor
1 TMDS clock *4 / Symbol per
clock/ Color depth factor
Bits per Color
8
10
12
16
TMDS clock channel from the HDMI RX and connects to the
reference clock to the IOPLL.
Reference clock to the RX CDR of RX transceiver.
Data Rate
Data rate <1 Gbps
1 Gbps< Data rate
<3.4 Gbps
Data rate >3.4 Gbps
• Data Rate <1 Gbps: For oversampling to meet
transceiver minimum data rate requirement.
• Data Rate >3.4 Gbps: To compensate for the TMDS bit
rate to clock ratio of 1/40 to maintain the transceiver
data rate to clock ratio at 1/10.
Note: Do not use a transceiver
clock. Your design will fail to fit if you place the
HDMI RX refclk on an
RX
Clock out recovered from the transceiver, and the frequency
varies depending on the data rate and symbols per clock.
RX transceiver clock out frequency = Transceiver data rate/
(Symbol per clock*10)
A free running 100 MHz clock for these components:
Color Depth Factor
1
1.25
1.5
2.0
RX Reference Clock
Frequency
5× TMDS clock frequency
TMDS clock frequency
4× TMDS clock frequency
pin as a CDR reference
RX
pin.
continued...
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Arria 10 Devices
25