Instruction Categories; Table 2-7. Category Listing - IBM A2 User Manual

User's Manual
A2 Processor

2.6 Instruction Categories

The Power ISA defines that each facility (including registers and fields therein) and instruction is in exactly
one category. Table 2-7 indicate the categories that are implemented by the A2 processor core.

Table 2-7. Category Listing

Implemented
by A2 Core
Yes Base
No Server
Yes Embedded
No Alternate Time Base
Yes Cache Specification
No Decimal Floating-Point
No Decorated Storage
No Embedded.Cache Debug
Yes Embedded.Cache Initialization
No Embedded.Device Control
No Embedded.Enhanced Debug
Yes Embedded.External PID
Yes Embedded.Hypervisor
Embedded.Hypervisor.LRAT
Yes Embedded.Little-Endian
Yes Embedded.Page Table
Yes Embedded.TLB Write Conditional E.TWC
No Embedded.Performance Monitor
Yes Embedded.Processor Control
Yes Embedded Cache Locking
Yes Embedded Multithreading
Embedded multiThread-
ing.Thread Management
No External Control
No External Proxy
Yes Floating-Point
Floating-Point.Record
No Legacy Move Assist
No Legacy Integer Multiply-
Accumulate1
No Load/Store Quadword
Yes Memory Coherence
No Move Assist
No Processor Compatibility
CPU Programming Model
Page 86 of 864
(Sheet 1 of 2)
Category Abbreviation
B
S
E
ATB
CS
DFP
DS
E.CD
E.CI
E.DC
E.ED
E.PD
E.HV
E.HV.LRAT
E.LE
E.PT
E.PM
E.PC
ECL
EM
EM.TM
EXC
EXP
FP
FP.R
LMV
LMA
LSQ
MMC
MA
PCR
Notes
Required for all implementations.
Required for server implementations.
Required for embedded implementations.
An additional time base; see Book II.
Specify a specific cache for some instructions; see Book II.
Decimal floating-point facilities.
Decorated storage facilities.
Provides direct access to cache data and directory content.
Instructions that invalidate the entire cache.
Embedded device control bus support.
Embedded enhanced debug facility; see Book III-E.
Embedded external PID facility; see Book III-E.
Embedded logical partitioning and hypervisor facilities.
Embedded hypervisor logical to real address translation.
Embedded little-endian page attribute; see Book III-E.
Embedded page table facility; see Book III-E.
Embedded TLB write conditional facility; see Book III-E.
Embedded performance monitor example; see Book III-E.
Processor control facility; see Book III-E.
Embedded cache locking facility; see Book III-E.
Embedded multithreading; see Book III-E.
Embedded multithreading thread management facility.
External control facility; see Book II.
External proxy facility; see Book III-E.
Floating-point facilities.
Floating-point instructions with Rc
Determine left most zero byte instruction.
Legacy integer multiply-accumulate instructions.
Load/store quadword instructions; see Book III-S.
Requirement for memory coherence; see Book II.
Move assist instructions.
Processor compatibility register.
=
1.
Version 1.3
October 23, 2012