Table 3-12. Location Of The Guard, Round, And Sticky Bits In The Ieee Execution Model - IBM A2 User Manual

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A2 Processor
After normalization, the intermediate result is rounded using the rounding mode specified by FPSCR[RN]. If
rounding results in a carry into C, the significand is shifted right one position and the exponent incremented
by one. This yields an inexact result and possibly also exponent overflow. Fraction bits to the left of the bit
position used for rounding are stored into the FPR, and low-order bit positions, if any, are set to zero.
Four user-selectable rounding modes are provided through FPSCR[RN] as described in Rounding on
page 139. For rounding, the conceptual Guard, Round, and Sticky bits are defined in terms of accumulator
bits. Table 3-12 shows the positions of the Guard, Round, and Sticky bits for double-precision and single-
precision floating-point numbers in the IEEE execution model.

Table 3-12. Location of the Guard, Round, and Sticky Bits in the IEEE Execution Model

Format Guard
Double G bit
Single 24
Rounding can be treated as though the significand were shifted right, if required, until the least significant bit
to be retained is in the low-order bit position of the FRACTION. If any of the Guard, Round, or Sticky bits is
nonzero, then the result is inexact.
Z1 and Z2, as defined in Rounding on page 139, can be used to approximate the result in the target format
when one of the following rules is used.
• Round to nearest
– Guard bit = 0
The result is truncated. (Result exact [GRX = 000] or closest to next lower value in magnitude [GRX =
001, 010, or 011])
– Guard bit = 1
Depends on Round and Sticky bits:
• Case a
If the Round or Sticky bit is 1 (inclusive), the result is incremented. (Result closest to next higher
value in magnitude [GRX = 101, 110, or 111])
• Case b
If the Round and Sticky bits are 0 (result midway between closest representable values) and if
the low-order bit of the result is 1, the result is incremented. Otherwise (the low-order bit of the
result is 0), the result is truncated (this is the case of a tie rounded to even).
• Round toward zero
Choose the smaller in magnitude of Z1 or Z2. If the Guard, Round, or Sticky bit is nonzero, the result is
inexact.
• Round toward +infinity
Choose Z1.
• Round toward –infinity
Choose Z2.
Where the result is to have fewer than 53 bits of precision because the instruction is a floating round to single-
precision or single-precision arithmetic instruction, the intermediate result is either normalized or placed in
correct denormalized form before being rounded.
FU Programming Model
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Round
R bit X bit
25 OR of 26:52, G, R, X
Sticky
Version 1.3
October 23, 2012