Table 2-1. Data Operand Definitions; Table 2-2. Alignment Effects For Storage Access Instructions - IBM A2 User Manual

Table 2-1. Data Operand Definitions

Storage Access Instruction Type
Byte (or String)
Halfword
Word (or Multiple)
Doubleword
Quadword (AXU only)
Double Quadword (AXU only)
Note: An "x" in an address bit position indicates that the bit can be 0 or 1 independent of the state of other bits in the address.
The alignment of the operand effective address of some storage access instructions might affect perfor-
mance; in some cases, it might cause an alignment exception to occur. For such storage access instructions,
the best performance is obtained when the storage operands are aligned. Table 2-2 summarizes the effects
of alignment on those storage access instruction types for which such effects exist. If an instruction type is not
shown in the table, there are no alignment effects for that instruction type.

Table 2-2. Alignment Effects for Storage Access Instructions

Storage Access Instruction Type
Integer cacheable load halfword
Integer cacheable store or caching
inhibited load/store halfword
Integer cacheable load word
Integer cacheable store or caching
inhibited load/store word
Integer cacheable load doubleword
Integer cacheable store or caching
inhibited load/store doubleword
Integer load/store multiple
Integer load/store string
AXU cacheable load halfword
AXU cacheable store or caching inhib-
ited load/store halfword
AXU cacheable load word
AXU cacheable store or caching inhib-
ited load/store word
AXU cacheable load doubleword
AXU cacheable store or caching inhib-
ited load/store doubleword
Version 1.3
October 23, 2012
Operand Length
8 bits
2 bytes
4 bytes
8 bytes
16 bytes
32 bytes
Broken into byte accesses if crosses 32-byte boundary (EA[59:63] = 0b11111); otherwise no
effect. (See notes.)
Broken into byte accesses if crosses 16-byte boundary (EA[60:63] = 0b1111); otherwise no
effect. (See notes.)
Broken into byte accesses if crosses 32-byte boundary (EA[59:63] > 0b11100); otherwise no
effect. (See notes.)
Broken into byte accesses if crosses 16-byte boundary (EA[60:63] > 0b1100); otherwise no
effect. (See notes.)
Broken into byte accesses if crosses 32-byte boundary (EA[59:63] > 0b11000); otherwise no
effect. (See notes.)
Broken into byte accesses if crosses 16-byte boundary (EA[60:63] > 0b1000); otherwise no
effect. (See notes.)
Broken into a series of word (4-byte) accesses until the last word is accessed. The load/store
multiple address must be word aligned. (See notes.)
Broken into a series of byte accesses until the last byte is accessed. (See notes.)
Broken into byte accesses if crosses 32-byte boundary (EA[59:63] = 0b11111); otherwise no
effect. (See notes.)
Broken into byte accesses if crosses 16-byte boundary (EA[60:63] = 0b1111); otherwise no
effect. (See notes.)
Broken into byte accesses if crosses 32-byte boundary (EA[59:63] > 0b11100); otherwise no
effect. (See notes.)
Broken into byte accesses if crosses 16-byte boundary (EA[60:63] > 0b1100); otherwise no
effect. (See notes.)
Broken into byte accesses if crosses 32-byte boundary (EA[59:63] > 0b11000); otherwise no
effect. (See notes.)
Broken into byte accesses if crosses 16-byte boundary (EA[60:63] > 0b1000); otherwise no
effect. (See notes.)
Addr[59:63] if Aligned
0bxxxxx
0bxxxx0
0bxxx00
0bxx000
0bx0000
0b00000
(Sheet 1 of 2)
Alignment Effects
User's Manual
A2 Processor
CPU Programming Model
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