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User's Manual
A2 Processor
forwarding invalidation snoops to target processors. This implies that the effective page number (EPN) in the
ERAT entries that pertain to the current 32-bit process need to have been created with zeros in the upper 32-
bits for an invalidate EPN compare to succeed and invalidation to occur.
6.11.10 32-Bit Mode ERAT Invalidate Local (Indexed) Instruction (eratilx)
The eratilx instruction is used to invalidate local ERAT entries that contain the virtual page number associ-
ated with the effective address of this instruction or, alternately, that contain certain specific values of param-
eters such as process ID, class, and so forth. This instruction has no effect on the underlying TLB structure (if
it exists in a particular MMU implementation).
This instruction operates essentially the same as the 64-bit mode version. However, in 32-bit mode, address
bits 0:31 of the effective address are forced to zero before comparison. This implies that the effective page
number (EPN) in the ERAT entries that pertain to the current 32-bit process needs to have been created with
zeros in the upper 32-bits for an invalidate EPN compare to succeed and invalidation to occur.
6.12 Page Reference and Change Status Management
When performing page management, it is useful to know whether a given memory page has been referenced,
and whether its contents have been modified. Note that this might be more involved than determining whether
a given TLB entry has been used to reference or change memory, because multiple TLB entries can translate
to the same memory page. If it is necessary to replace the contents of some memory page with other
contents, a page that has been referenced (accessed for any purpose) is more likely to be maintained than a
page that has never been referenced. If the contents of a given memory page are to be replaced and the
contents of that page have been changed, the current contents of that page must be written to backup phys-
ical storage (such as a hard disk) before replacement.
Similarly, when performing TLB management, it is useful to know whether a given TLB entry has been refer-
enced. When making a decision about which entry of the TLB to replace to make room for a new entry, an
entry that has never been referenced is a more likely candidate to be replaced.
The A2 core does not automatically record references or changes to a page or TLB entry. Instead, the inter-
rupt mechanism can be used by system software to maintain reference and change information for TLB
entries and their associated pages, respectively.
Execute, read and write access control exceptions can be used to allow software to maintain reference and
change information for a TLB entry and for its associated memory page. The following description explains
one way in which system software can maintain such reference and change information.
The TLB entry is originally written into the TLB with its access control bits (UX, SX, UR, SR, UW, and SW) off.
The first attempt of application code to use the page therefore causes an access control exception and a
corresponding instruction or data storage interrupt. The interrupt handler can choose to record the reference
to the TLB entry and to the associated memory page in a software table, and then turns on the appropriate
access control bit and referenced bit, thereby indicating that the particular TLB entry has been referenced. An
initial read from the page is handled by turning on the appropriate UR or SR access control bit and setting the
R bit, leaving the page "read-only" and referenced. Subsequent read accesses to the page via that TLB entry
proceed normally.
Memory Management
Version 1.3
Page 228 of 864
October 23, 2012
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