Guest Data Exception Address Register (Gdear); Table 7-2. Interrupt Types And Associated Offsets - IBM A2 User Manual

User's Manual
A2 Processor

7.5.14 Guest Data Exception Address Register (GDEAR)

The GDEAR contains the address that was referenced by a load, store, or cache management instruction
that caused an alignment, data TLB miss, or data storage exception when the interrupt is directed to the
guest state.
The GDEAR can be written from a GPR using mtspr and can be read into a GPR using mfspr. GDEAR is
also accessed by reading DEAR when in the guest state (MSR[GS] = 1).
Register Short Name:
Decimal SPR Number:
Initial Value:
Slow SPR:
Guest Supervisor Mapping:
Bits Field Name
0:63 GDEAR
Interrupt Fixed Offsets
An Interrupt offset specifies the 12-bit low-order effective address offset for each interrupt type. The value is
the offset from the base address provided by either the IVPR (see Interrupt Vector Prefix Register (IVPR) on
page 318) or the GIVPR (see Guest Interrupt Vector Prefix Register (GIVPR) on page 318). The interrupt
effective address is either:
IVPR || 12-bit Interrupt Offset
0:51
or
GIVPR || 12-bit Interrupt Offset
0:51
IVPR is used if MSR[GS] is set to 0, otherwise GIVPR is used.
Table 7-2 identifies the specific interrupt offsets associated with each interrupt type.

Table 7-2. Interrupt Types and Associated Offsets

Offset
0x040 Debug
0x020 Critical input
0x000 Machine check
0x060 Data storage
0x080 Instruction storage
0x0A0 External input
0x0C0 Alignment
CPU Interrupts and Exceptions
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GDEAR
381
0x0000000000000000
N
Y
Initial
Value
0x0 Guest Data Exception Address Register
The GDEAR contains the address that was referenced by a load, store , or cache manage-
ment instruction that caused an alignment, data TLB miss, or data storage interrupt when
directed to the guest state.
(Sheet 1 of 2)
Read Access:
Write Access:
Duplicated for Multithread:
Notes:
Scan Ring:
Description
Interrupt Type
Priv
Priv
Y
HM
func
Version 1.3
October 23, 2012