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3.5.2 Execution Model for Multiply-Add Type Instructions
The A2 core provides a special form of instruction that performs up to three operations in one instruction (a
multiplication, an addition, and a negation). With this added capability comes the special ability to produce a
more exact intermediate result as input to the rounder. 32-bit arithmetic is similar except that the FRACTION
field is smaller.
Multiply-add significand arithmetic is considered to be performed with a floating-point accumulator having the
following format, where bits 0:106 comprise the significand of the intermediate result.
Table 3-13. Multiply-Add 64-Bit Execution Model
S
C
L
0 1
The first part of the operation is a multiplication. The multiplication has two 53-bit significands as inputs, which
are assumed to be prenormalized, and produces a result conforming to the above model. If there is a carry
out of the significand (into the C bit), then the significand is shifted right one position, shifting the L bit (leading
unit bit) into the most significant bit of the FRACTION and shifting the C bit (carry out) into the L bit. All 106
bits (L bit, the FRACTION) of the product take part in the add operation. If the exponents of the two inputs to
the adder are not equal, the significand of the operand with the smaller exponent is aligned (shifted) to the
right by an amount that is added to that exponent to make it equal to the other input's exponent. Zeros are
shifted into the left of the significand as it is aligned, and bits shifted out of bit 105 of the significand are ORed
into the X' bit. The add operation also produces a result conforming to the above model with the X' bit taking
part in the add operation.
The result of the addition is then normalized, with all bits of the addition result, except the X' bit, participating
in the shift. The normalized result serves as the intermediate result that is input to the rounder.
For rounding, the conceptual Guard, Round, and Sticky bits are defined in terms of accumulator bits.
Table 3-14 shows the positions of the Guard, Round, and Sticky bits for double-precision and single-precision
floating-point numbers in the multiply-add execution model.
Table 3-14. Location of Guard, Round, and Sticky Bits in the Multiply-Add Execution Model
Format
Guard
Double
53
Single
24
The rules for rounding the intermediate result are the same as those given in Execution Model for IEEE Oper-
ations on page 141.
If the instruction is a floating negative multiply-add or floating negative multiply-subtract, the final result is
negated.
3.6 Floating-Point Instructions
Primary opcode 63 is used for the double-precision arithmetic instructions and miscellaneous instructions,
such as the Floating-Point Status and Control Register Manipulation instructions. Primary opcode 59 is used
for the single-precision arithmetic instructions.
Version 1.3
October 23, 2012
FRACTION
Round
54
OR of 55:105, X'
25
OR of 26:105, X'
User's Manual
A2 Processor
X'
105 106
Sticky
FU Programming Model
Page 143 of 864
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