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CompactFlash Memory Card Product Manual
5.5.9
Status & Alternate Status Registers
(Address 1F7[177]&3F6[376];
Offsets 7 & Eh)
These registers return the CompactFlash Memory
Card status when read by the host. Reading the
Status register does clear a pending interrupt
while reading the Auxiliary Status register does
D7
D6
BUSY
RDY
Bit 7 (BUSY)
The busy bit is set when the CompactFlash Memory Card has access to the command buffer and
registers and the host is locked out from accessing the command register and buffer. No other bits
in this register are valid when this bit is set to a 1.
Bit 6 (RDY)
RDY indicates whether the device is capable of performing CompactFlash Memory Card operations.
This bit is cleared at power up and remains cleared until the CompactFlash Card is ready to accept
a command.
Bit 5 (DWF)
This bit, if set, indicates a write fault has occurred.
Bit 4 (DSC)
This bit is set when the CompactFlash Memory Card is ready.
Bit 3 (DRQ)
The Data Request is set when the CompactFlash Memory Card requires that information be
transferred either to or from the host through the Data register.
Bit 2 (CORR)
This bit is set when a Correctable data error has been encountered and the data has been
corrected. This condition does not terminate a multi-sector read operation.
Bit 1 (IDX)
This bit is always set to 0.
Bit 0 (ERR)
This bit is set when the previous command has ended in some type of error. The bits in the Error
register contain additional information describing the error.
5.5.10
Device Control Register
(Address - 3F6[376]; Offset Eh)
This register is used to control the CompactFlash
Memory Card interrupt request and to issue an
D7
D6
X
X
Bit 7
This bit is an X (don't care).
Bit 6
This bit is an X (don't care).
Bit 5
This bit is an X (don't care).
Bit 4
This bit is an X (don't care).
Bit 3
This bit is ignored by the CompactFlash Memory Card.
Bit 2 (SW Rst)
This bit is set to 1 in order to force the CompactFlash Memory Card to perform an AT Disk
controller Soft Reset operation. This does not change the PCMCIA Card Configuration Registers
(4.3.2 to 4.3.5) as a hardware Reset does. The Card remains in Reset until this bit is reset to '0'.
Bit 1 (-IEn)
The Interrupt Enable bit enables interrupts when the bit is 0. When the bit is 1, interrupts from the
CompactFlash Memory Card are disabled. This bit also controls the Int bit in the Configuration
and Status Register. This bit is set to 1 at power on and Reset.
Bit 0
This bit is ignored by the CompactFlash Memory Card.
54
not. The meaning of the status bits are described as
follows:
D5
D4
DWF
DSC
ATA soft reset to the card. The bits are defined as
follows:
D5
D4
X
X
SanDisk CompactFlash Memory Card Product Manual © 1998 SANDISK CORPORATION
D3
D2
DRQ
CORR
D3
D2
1
SW Rst
D1
D0
0
ERR
D1
D0
-IEn
0
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