Status & Alternate Status Registers; 5.2.10 Device Control Register - SanDisk SDIB-4 Product Manual

FlashDrive Product Manual
5.2.9 Status & Alternate Status Registers
These registers return the FlashDrive status when
read by the host. Reading the Status register does
clear a pending interrupt while reading the
D7 D6
BUSY RDY
Bit 7 (BUSY) The busy bit is set when the FlashDrive has access to the command buffer and registers and the
host is locked out from accessing the command register and buffer. No other bits in this register
are valid when this bit is set to a 1.
Bit 6 (RDY) RDY indicates whether the device is capable of performing FlashDrive operations. This bit is
cleared at power up and remains cleared until the FlashDrive is ready to accept a command.
Bit 5 (DWF) This bit, if set, indicates a write fault has occurred.
Bit 4 (DSC) This bit is set when the FlashDrive is ready.
Bit 3 (DRQ) The Data Request is set when the FlashDrive requires that information be transferred either to or
from the host through the Data register.
Bit 2 (CORR) This bit is set when a Correctable data error has been encountered and the data has been
corrected. This condition does not terminate a multi-sector read operation.
Bit 1 (IDX) This bit is always set to 0.
Bit 0 (ERR) This bit is set when the previous command has ended in some type of error. The bits in the Error
register contain additional information describing the error.

5.2.10 Device Control Register

This register is used to control the FlashDrive
interrupt request and to issue an ATA soft reset to
the card. The bits are defined as follows:
D7 D6
X X
Bit 7 This bit is an X (don't care).
Bit 6 This bit is an X (don't care).
Bit 5 This bit is an X (don't care).
Bit 4 This bit is an X (don't care).
Bit 3 This bit is ignored by the FlashDrive.
Bit 2 (SW Rst) This bit is set to 1 in order to force the FlashDrive to perform an AT Disk controller Soft Reset
operation. The Card remains in Reset until this bit is reset to '0.'
Bit 1 (-IEn) The Interrupt Enable bit enables interrupts when the bit is 0. When the bit is 1, interrupts from the
FlashDrive are disabled. This bit also controls the Int bit in the Configuration and Status Register.
This bit is set to 1 at power on and Reset.
Bit 0 This bit is ignored by the FlashDrive.
34
Auxiliary Status register does not. The meaning of
the status bits are described as follows:
D5 D4
DWF DSC
D5 D4
X X
D3 D2
DRQ CORR
D3 D2
1 SW Rst
FlashDrive Product Manual © 1999 SANDISK CORPORATION
D1 D0
0 ERR
D1 D0
-IEn 0