Table 2-15. Phb Hardware Configuration - Motorola MVME5100 Programmer's Reference Manual

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
2
Function
PCI 64-bit Enable
PPC Register Base
MPIC Interrupt Type
PPC Arbiter Mode
PCI Arbiter Mode
PPC:PCI Clock Ratio
2-50
edge of CLK after RST_ has been released. All of the sampled pins are
cascaded with several layers of registers to eliminate problems with hold
time.
Table 2-15 summarizes the hardware configuration options that relate to
the PHB.

Table 2-15. PHB Hardware Configuration

Sample Pin(s)
REQ64_
RD[5]
RD[7]
RD[8]
RD[9]
RD[10:12]
Sampled Meaning
State
0 64-bit PCI Bus
1 32-bit PCI Bus
0 Register Base = $FEFF0000
1 Register Base = $FEFE0000
0 Parallel Interrupts
1 Serial Interrupts
0 Disabled
1 Enabled
0 Disabled
1 Enabled
000 Reserved
100
010
110
001
101 Reserved
011
111 Reserved
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1:1
2:1
3:1
3:2
5:2