Software Considerations; Programming Rom/Flash Devices; Writing To The Control Registers - Motorola MVME5100 Programmer's Reference Manual

System Memory Controller (SMC)
p0_tben
3

Software Considerations

Programming ROM/Flash Devices

Writing to the Control Registers

3-74
When the tben_en bit is cleared, p1_tben has no effect on any
pin.
When the tben_en bit is set, the ERCS_ output pin becomes the
P1_TBEN output pin and it tracks the value on p0_tben. When
p0_tben is 0, the P0_TBEN pin is low and when p1_tben is 1,
the P0_TBEN pin is high.
When the tben_en bit is cleared, p0_tben has no effect on any
pin.
Note that when tben_en is high, L2CLM_ cannot be driven by
an external L2 cache controller and no External Register Set
devices can be controlled.
This section contains information that will be useful in programming a
system that uses the Hawk.
Those who program devices to be controlled by the Hawk should make
note of the address mapping that is shown in
For example, when using 8-bit devices, the code will be split so that every
other 4-byte segment goes in each device.
Software should not change control register bits that affect SDRAM
operation while SDRAM is being accessed. Because of pipelining,
software should always make sure that the two accesses before and after
the updating of critical bits are not SDRAM accesses.
A possible scenario for trouble would be to execute code out of SDRAM
while updating the critical SDRAM control register bits. The preferred
method is to be executing code out of ROM/Flash and avoiding SDRAM
accesses while updating these bits.
Table 3-3
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and in Table 3-4.