Nvram/Rtc & Watchdog Timer; Table 1-15. M48T37V Access Registers - Motorola MVME5100 Programmer's Reference Manual

Product Data and Memory Maps
1
NVRAM/RTC & Watchdog Timer
Required of
Optional
This Group
Optional
1-28
The MVME5100's NVRAM/RTC and Watchdog Timer functions are
supplied by an M48T37V device and is fully compliant with the
PowerPlusII internal programming configuration. The M48T37V provides
32K of non-volatile SRAM, a time-of-day clock, and a watchdog timer.
Accesses to the M48T37V is accomplished via three registers: the
NVRAM/RTC Address Strobe 0 Register, the NVRAM/RTC Address
Strobe 1 Register, and the NVRAM/RTC Data Port Register. The
NVRAM/RTC Address Strobe 0 Register latches the lower 8 bits of the
address and the NVRAM/RTC Address Strobe 1 Register latches the upper
5 bits of the address

Table 1-15. M48T37V Access Registers

Offset Address
80C8
80D0
80D8
The NVRAM and RTC is accessed through the above three registers.
When accessing an NVRAM/RTC location, perform the following
procedure:
1. Write the low address (A7-A0) of the NVRAM to the
NVRAM/RTC STB0 register,
2. Write the high address (A15-A8) of the NVRAM to the
NVRAM/RTC STB1 register, and
3. Then read or write the NVRAM/RTC Data Port.
Refer to the M48T37V Data Sheet for additional details and programming
information.
Function
NVRAM/RTC Address Strobe 0 (A7-A0)
NVRAM/RTC Address Strobe 1 (A15-A8)
NVRAM/RTC Data Register
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