Timer Destination Registers; External Source Vector/Priority Registers - Motorola MVME5100 Programmer's Reference Manual
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Also See for MVME5100:
- Programmer's reference manual (270 pages) ,
- Manual (127 pages) ,
- Installation & use manual (107 pages)
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
Timer Destination Registers
2
Offset
Bit
3
1
Name
Operation
Reset
External Source Vector/Priority Registers
Offset
Bit
3
1
Name
Operation
Reset
2-122
3
2
2
2
2
2
2
2
2
0
9
8
7
6
5
4
3
2
R
$00
This register indicates the destinations for this timer's interrupts. Timer
interrupts operate in the Directed delivery interrupt mode. This register
may specify multiple destinations (multicast delivery).
P1
PROCESSOR 1. The interrupt is directed to processor 1.
P0
PROCESSOR 0. The interrupt is directed to processor 0.
Int Src 1-> Int Src15 - $10020 -> $101E0
3
2
2
2
2
2
2
2
2
0
9
8
7
6
5
4
3
2
EXTERNAL SOURCE VECTOR/PRIORITY
R
$000
Timer 0 - $01130
Timer 1 - $01170
Timer 2 - $011B0
Timer 3 - $011F0
2
2
1
1
1
1
1
1
1
1
0
9
8
7
6
5
4
3
TIMER DESTINATION
R
$00
$00
Int Src 0 - $10000
2
2
1
1
1
1
1
1
1
1
0
9
8
7
6
5
4
3
PRIOR
R/W
$0
$00
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1
1
1
2
1
0 9 8 7 6 5 4 3 2 1 0
R
R
$00
1
1
1
2
1
0 9 8 7 6 5 4 3 2 1 0
VECTOR
R
R/W
$00
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