Processor Memory Map - Motorola MVME5100 Programmer's Reference Manual

Table 1-2. Default Processor Memory Map (Continued)
Processor Address
Start End
FEF9 0000 FEFE FFFF
FEFF 0000 FEFF FFFF
FF00 0000 FFEF FFFF
FFF0 0000 FFFF FFFF
Note
For an example of the CHRP memory map refer to the following table. For
detailed processor memory maps, including suggested CHRP- and PREP-
compatible memory maps, refer to the Hawk related portion of this
manual.

Processor Memory Map

The following table describes a suggested CHRP Memory Map from the
point of view of the processor. This memory map is an alternative to the
PREP memory map. Note: in all recommended CHRP maps, the beginning
of PCI Memory Space is determined by the end of DRAM rounded up to
the nearest 256MB-boundry as required by CHRP. For example, if
memory was 1G on the baseboard and 192MB on a mezzanine, the
beginning of PCI memory would be rounded up to address 0x50000000
(1G + 256M).
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Size
384KB
64KB
15MB
1MB
The first 1MB of ROM/FLASH Bank A (soldered Flash up
to 8MB) appears in this range after a reset if the rom_b_rv
control bit in the SMC's ROM B Base/Size register is
cleared. If the rom_b_rv control bit is set, this address range
maps to ROM/FLASH Bank B (socketed 1MB Flash).
Definition
Not Mapped
PCI Host Bridge (PHB) Registers
Not Mapped
ROM/FLASH Bank A or Bank B (See
Note)
Memory maps
1
1-5