Data Parity Error Log Register - Motorola MVME5100 Programmer's Reference Manual

System Memory Controller (SMC)

Data Parity Error Log Register

Address
Bit
3
Name
Operation
Reset
3-60
READ ONLY
dpelog dpelog is set when a parity error occurs on the PPC60x
data bus during a PPC60x data cycle whose parity the
SMC is qualified to check. It is cleared by writing a one to
it or by power-up reset.
dpe_tt0-4 dpe_tt is the value that was on the TT0-TT4 signals when
the dpelog bit was set.
DPE_DP DPE_DP is the value that was on the DP0-DP7 signals
when the dpelog bit was set.
dpe_ckall When dpe_ckall is set, the Hawk checks data parity on all
cycles in which TA_ is asserted. When dpe_ckall is
cleared, the Hawk checks data parity on cycles when TA_
is asserted only during writes to the Hawk.
Note that the Hawk does not check parity during cycles in
which there is a qualified ARTRY_ at the same time as the
TA_.
dpe_me When dpe_me is set, the transition of the dpelog bit from
false to true causes the Hawk to pulse its machine check
interrupt request pin (MCHK0_) true. When dpe_me is
cleared, the Hawk does not assert its MCHK0_ pin based
on the dpelog bit.
GWDP The GWDP0-GWDP7 bits are used to invert the value that
is driven onto DP0-DP7 respectively during reads to the
Hawk. This allows test software to generate wrong (even)
parity on selected byte lanes. For example, to create a
parity error on DH24-DH31 and DP3 during Hawk reads,
software should set GWDP3.
$FEF80068
DPE_DP
0 P
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GWDP
READ/WRITE
0 PL