L2 Cache Sram Size; Cache Speed; Flash Memory - Motorola MVME5100 Programmer's Reference Manual

Product Data and Memory Maps
1

L2 Cache SRAM Size

Cache Speed

FLASH Memory

1-10
checking may be disabled by programming Max accordingly. Refer to the
MPC750 or the MPC7400 RISC Microprocessor Users Manual and
Chapter 3 of this manual for more information on programming cache.
The L2 cache port will support SRAM configurations of 1MB or 2MB.
The L2 cache size is defined by reading the Vital Product Data (VPD)
SROM and programming the L2SIZ bits in the processor's Cache Control
Register (L2CR).
The MPC7400 and the MPC750 cache port provides the clock for the
synchronous SRAMs. This clock is generated by dividing the processor
core frequency. Available core-to-cache dividers range from 1 to 4, in .5
steps for the MPC7400. For the MPC750, the core-to-cache dividers range
from 1 to 3 in .5 steps.
The core-to-cache ratio is selected by reading the VPD SROM and
programming the L2CLK bits of the processor's Cache Control Register.
Refer to the MPC7400 RISC Microprocessor Users Manual or the
MPC750 RISC Microprocessor Users Manual as listed in
Related Documentation
The MVME5100 contains two banks of FLASH memory. Bank B consists
of two 32-pin devices that can be populated with 1MB of FLASH memory.
Only 8-bit writes are supported for this bank. Bank A has 4 16-bit Smart
Voltage FLASH SMT devices. With the 16 Mbit FLASH devices, the
FLASH size is 8MB. With 32 Mbit FLASH devices, the FLASH size is
16MB. Only 32-bit writes are supported for this bank of FLASH. There is
a jumper to tell the Hawk ASIC where to fetch the reset vector. When the
jumper is installed, the Hawk ASIC maps 0xfff00100 to these sockets
(Bank B). Flash memory characteristics are fully compatible with those
specified further on in this programmer's guide for Flash Blocks
A and B.
for more information.
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Appendix A,