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Appendix C
Using Your PC-LPM-16 (Non-PnP) Board
Functional Changes
Data FIFO Size
Dummy reads to A/D
and FIFO high-byte
and low-byte registers
after clearing data
FIFO
ADC FIFO Data
Reading Order
Overflow Error Bit
Location
Overrun Error Bit
Location
Data Error Bit
Location
5 and 12 V Supply
Fuses
-12 V Supply Power
Requirements
INL
Gain Error, 2.8 V or
to 10 V Range
Calibration Time
Overvoltage
Protection or Analog
Input Powered Off
PC-LPM-16/PnP User Manual
Table C-1.
Comparison of Characteristics (Continued)
Legacy PC-LPM-16
16 words
Required
Low byte before
high byte preferred
Status Register 1,
bit 1
Not implemented
Not implemented
Nonresettable
0 mA
Performance Specification Changes
1 LSB max
3 LSB typ,
7 LSB max
700 s typ
45 V
Revised PC-LPM-16
512 words
Not required, but
allowed
Low byte must be
read before high
byte
Status Register 1,
bit 1
Not implemented
Not implemented
Self-resetting
15 mA typ
0.5 LSB max
2 LSB typ,
4 LSB max
10 ms typ
35 V
C-2
PC-LPM-16PnP
256 words
Not required, but
allowed
Low byte must be
read before high
byte
Status Register 2,
bit 1
Status Register 2,
bit 0
Status Register 1,
bit 1
Self-resetting
15 mA typ
0.5 LSB max
2 LSB typ,
4 LSB max
10 ms typ
35 V
National Instruments Corporation
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