Table of Contents
Advertisement
Chapter 3
Theory of Operation
Analog Input and Data Acquisition Circuitry
PC I/O
Channel
Interface
Interrupt
Interface
1 MHz
PC-LPM-16/PnP User Manual
request lines available: IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, and IRQ9.
The PC-LPM-16PnP generates interrupts in three different situations:
•
When an A/D conversion generates data that can be read from FIFO
•
When an active low-level signal is detected on the EXTINT* line
•
When a rising-edge signal is detected on counter 2 output
The PC-LPM-16PnP individually enables and clears each one of these
interrupts. For more detailed information on generating interrupts
externally, see the EXTINTEN bit of the Command Register 1
description in Appendix D, Register-Level Programming.
The PC-LPM-16PnP has 16 channels of analog input with 12-bit
A/D conversion. Using the timing circuitry, the PC-LPM-16PnP can
also automatically time multiple A/D conversions. Figure 3-3 shows a
block diagram of the analog input and data acquisition circuitry.
8
256-Word
FIFO
A/D RD
CONVAVAIL
CLK0
MSM82C53
Figure 3-3. Analog Input and Data Acquisition Circuitry Block Diagram
12-Bit
Sampling
Buffer
ADC
A/D
Data
OUT0
A/D Timing
3-4
Input Mux
16-Channel
Single-Ended
16
ACH<0..15>
4
Scanning Counter
EXTCONV*
National Instruments Corporation
Advertisement
Table of Contents
