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Chapter 4
Signal Connections
V
CLK
V
V
GATE
V
V
OUT
V
PC-LPM-16/PnP User Manual
MSM82C53 digital input specifications (referenced to DGND):
•
V
input logic high voltage
IH
•
V
input logic low voltage
IL
•
Input load current
MSM82C53 digital output specifications (referenced to DGND):
•
V
output logic high voltage
OH
•
V
output logic low voltage
OL
•
I
output source current, at V
OH
•
I
output sink current, at V
OL
IH
IL
t gsu
IH
IL
OH
OL
t sc
t pwh
t pwl
t gsu
t gh
t gwh
t gwl
t outg
t outc
The GATE and OUT signals in Figure 4-7 are referenced to the rising
edge of the CLK signal.
OH
OL
t sc
t gh
t gwh
t outg
clock period
clock high level
clock lowlevel
gate setup time
gate hold time
gate high level
gate low level
output delay from clock
output delay from gate
Figure 4-7. General-Purpose Timing Signals
4-12
2.2 V min
0.8 V max
10.0 A max
3.7 V min
0.45 V max
1.0 mA max
4.0 mA max
t pwh
t pwl
t gwl
t outc
125 ns min
60 ns min
60 ns min
60 ns min
60 ns min
60 ns min
60 ns min
60 ns min
60 ns min
National Instruments Corporation
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