I 2 C Bus For Vrm - Supermicro X10DRT-H User Manual

X10DRT-H/HIBF Motherboard User's Manual
I C Bus for VRM
2
Jumpers JVRM1 and JVRM2 allow the BMC
or the PCH to access CPU and memory VRM
controllers. See the table on the right for jumper
settings.
LE1
JB1 A
1 C
UID
JUIDB1
1
3
QSFP
1
JB3
1
JB2
3
JP1
1 JP2
JBT1:
CMOS
CLEAR
MH1
COM1
VGA
JVGA JCOM1
JIB1
LAN2 LAN1
C
LEDBMC
JUSBRJ45
JSTBY1
1
JPB1:BMC
1-2:ENABLE
2-3:DISABLE
BT1
B
1 1
JSD2
CPU1
CLOSE 1st
+
OPEN 1st
CPU2
CLOSE 1st
OPEN 1st
2-28
I2C Bus for VRM
Jumper Settings
Jumper Setting
1-2
2-3
A. JVRM1
B. JVRM2
A
Definition
Enabled (Default)
Disabled