Sony SCD-C222ES Service Manual page 74

SCD-C222ES
• MAIN BOARD IC901 CXP974096-001R (CPU)
Pin No. Pin Name
1 MODE DF
2 AMUTE
3 DOCTRL
4 LAT DAC
5 DATA DAC
6 CLK DAC
7 FCS JMP 1
8 FCS JMP 2
9 SENS CD
10 XCS DRAM
11 XCS IO
12 XCS DVD
13 VSS
14 to 21 D0 to D7
22 INT0 DVD
23 INT1 DVD
24 T SENS
25 MON DVD
26 DATA CD
27 XLAT CD
28 A1IN
29 COUT CD
30 IN SW
31 OUT SW
32 MIRR RF
33 SUBQ CD
34 SCOR CD
35 SQCLK CD
36 —
37 CLOK CD
38 XRST
39 VSS
40 XTAL
41 EXTAL
42 VDD
43 SPDA
44 APDO
45 MUTE DSD
46 XMSLAT
47 READY DSD
48 SDIN DSD
49 SOUT DSD
74
I/O
SACD/CD mode selection signal output to the muting circuit
O
"L": CD mode, "H": SACD mode
O
Muting on/off signal output to the analog line circuit "L": muting on
Digital out on/off control signal output to the CXD3068Q (IC509)
O
"L": digital out off, "H": digital out on
O
Serial data latch pulse signal output to the D/A converter Not used (open)
O Serial data output to the D/A converter Not used (open)
O
Serial data transfer clock signal output to the D/A converter Not used (open)
O
Focus jump 1 signal output to the BA5983FP (IC502)
O
Focus jump 2 signal output to the BA5983FP (IC502)
I Internal status (SENSE) signal input from the CXD3068Q (IC509)
O
Chip select signal output to the D-RAM Not used (pull up)
O
Chip select signal output to the I/O expander (IC902)
O
Chip select signal output to the CXD1882R (IC701)
— Ground terminal (digital system)
I/O
Two-way data bus with the CXD1882R (IC701) and I/O expander (IC902)
I
Interrupt signal input from the CXD1882R (IC701)
I
Interrupt signal input from the CXD1882R (IC701)
I Disc tray status detection signal input from the table sensor (D10)
I
Monitor signal input terminal Not used (open)
O
Serial data output to the CXD3068Q (IC509)
O
Serial data latch pulse signal output to the CXD3068Q (IC509)
I
Sircs remote control signal input of the CONTROL A1II (J381)
I
Numbers of track counted signal input from the CXD3068Q (IC509)
I
Loading in switch input terminal "L": loading in Not used (fixed at "H")
I
Loading out switch input terminal "L": loading out Not used (fixed at "H")
I
Mirror signal input from the CXD3068Q (IC509)
I
Subcode Q data input from the CXD3068Q (IC509)
I
Subcode sync (S0+S1) detection signal input from the CXD3068Q (IC509)
O
Subcode Q data reading clock signal output to the CXD3068Q (IC509)
—
Not used (open)
O
Serial data transfer clock signal output to the CXD3068Q (IC509)
System reset signal input from the reset signal generator (IC905) "L": reset
I
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
—
Ground terminal (digital system)
I System clock input terminal (20 MHz)
O
System clock output terminal (20 MHz)
—
Power supply terminal (+3.3V) (digital system)
O
Spindle motor (M3) control signal output to the BA5912AFP (IC512)
O Output terminal for offset adjustment of APEO (<z/. pin of CXD1882R (IC701))
Muting on/off signal output to the DSD decoder (IC801) and CXD9647R (IC803)
O
"H": muting on
O
Serial data latch pulse signal output to the DSD decoder (IC801)
I
Ready signal input from the DSD decoder (IC801) and CXD9647R (IC803) "L": ready
I
Serial data input from the DSD decoder (IC801) and CXD9647R (IC803)
O
Serial data output to the DSD decoder (IC801) and CXD9647R (IC803)
Description