Oki OKIPAGE 10ex Maintenance Manual page 209

3.4 EEPROM Control
The 93LC46A is an electrical erasable/programmable ROM of 64-bit x 16-bit configuration. Data
input to and output from the ROM are bidirectionally transferred in units of 16 bits through a serial
I/O port (SSTXD-P) in serial transmission synchronized with a clock signal from the CPU.
The EEPROM operates in the following instruction modes
The EEPROM operates in the following instruction modes
Instruction
Read (READ)
Write Enabled (WEN)
Write (WRITE) 1
Write All Address (WRAL)
Write Disabled (WDS)
Erase
Chip Erasable (ERAL)
Write cycle timing (WRITE)
CS
SK
DI
DO
HIGH-Z
Read cycle timing (READ)
CS
SK
DI
DO
HIGH-Z
40990901TH Rev.1
SSTXD-P
154
CPU
150
151
Start bit
1
1
01
1
1
1
1
1 2 4
A5 A4
1 0 1
1 2 4
A5 A4
1 1 0
3
DI
1
EEPRMCS0-P
CS
EEPRMCLK-P
Operation
code
10
00
A5 to A0 D15 to D0
00
00
11
00
9 10
A1 A0 D15 D14
9 10
A1 A0
0 D15 D14
DO
4
SK
2
Address Data
A5 to A0
11XXXX
01XXXX D15 to D0
00XXXX
A5 to A0
10XXXX
Min. 450 ns
STATUS
25
D1 D0
Max. 500 ns
BUSY READY
Max. 10 ms
25 26
D1 D0 D15 D14
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