Block Diagram Of The Vsp9412A; Description - Daewoo DTH-29U3 Service Manual

CP830F Service Manual

4.2.1 BLOCK DIAGRAM OF THE VSP9412A

Data
7
Acquisition
CVBS
(Y/C)
3
CVBS
(OUT)
Source Select
2
A/D Conversion
R/Cr
Color Decoder
2
G/Y
Frontend Sync
2
B/Cb
Soft Mix
2
FBL
8
ITU 656
CLK 656
cybso1 cybso2 cybso3 reset
cybs1
ADC1
cybs2
(2)
Soruce
cybs3
Select
cybs4
cybs5
(1)
ADC2
cybs6
(2)
cybs7
ADCR
min1
(12)
gin1
ADCG
Soruce
bin1
(13)
Select
fbt1
ADCB
rin2
(16)
(14)
gin2
bin2
ADCF
(15)
fbt2
656clk
656io0
656io1
ITO656
656io2
Decoder
656io3
656io4
(41)
656io5
656io6
656io7
CLKF2PAD
656hinf 656vln
clkf20

4.2.2 DESCRIPTION

Integrated Video Matrix switch
- Up to seven CVBS inputs, up to two Y/C inputs,
- Up to three CVBS outputs (even when Y/C input)
- 9 bit amplitude resolution for CVBS, Y/C A/D converter
- AGC (Automatic Gain Control)
Input
Processing
Noise
Reduction
Clock
Generation
20.25 MHz
h50 v50 v xout xin
Y
CVBS Frontend
U,V
(4/4/6/7/8)
Soft-mix
(30)
Y
U,V
RBB Frontend
CLKB36
CLKF20
PC
test-controller,
interface
memory hist
(56)
tclk tms adntd scl sda
Memory Display
Processing
Hor. Scaling
Mem. Controller
Panorama
Field Memory
Peaking, CTI
4:2:2 Format
2
I C
SCL
free-running
Clock generation
clocks
(9/10/11)
Iine-locked
clocks
Channel Sample tate
mix Converter
(31) (33/34)
Noise
measurerrent
(32)
PRIMUS
VSP94x2A
Peaking/DCTI/delzly
Panorama Scaler
(42/43/44/57)
(45/46/49/50)
line locked or
free-running
8 ITU656 Encoder
-20-
Output
Processing
Display Sync
D/A conversion
Oversampling
(9402/9432)
B
Digital Output
(9412/9442)
SDA
Output
memory
Data
controller
Controller
(39)
(55)
Noise
reduction
(35/36/37/38) eDRAM
Y DAC (52)
U DAC (53)
V DAC (54)
(51)
HOUT
VOUT
CLK27
Y
Cr
Cb
Digital 656
CLK 656
Output
clkout
Sync
vout
Controller
(40)
hout
ayout
auout
avout