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BIOS
DRAM RAS# to CAS# Delay
It allows you to insert a delay between the RAS (Row Address Strobe) and
CAS (Column Address Strobe) signals. This delay occurs when the SDRAM
is written to, read from or refreshed. Reducing the delay improves the
performance of the SDRAM.
Setting: 3 (Default), 2.
DRAM Data Integrity Mode
Setting: Non-ECC (Default), ECC.
MGM Core Frequency
This Select equates are used for determining the FSB MEM/GFX LOW/GFX
high core frequency DRAM data integrity mode.
Setting: Auto Max 266MHz (Default), 100MHz-533MHz,
Auto Max 400/333MHz, Auto Max 533/333MHz.
System BIOS Cacheable
The setting of Enabled allows caching of the system BIOS ROM at F000h-
FFFFFh for better system performance. However, if any program writes to
this memory area, a system error may result.
Setting: Disabled, Enabled (Default).
Video BIOS Cacheable
The Setting Enabled allows caching of the video BIOS ROM at C0000h-
F7FFFh for better video performance. However, if any program writes to this
memory area, a system error may result.
Setting: Disabled, Enabled (Default).
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