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ROHS EmETXe-i9652 User Manual

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EmETXe-i9652
COM Express CPU Module
User's Manual
Version 1.2
2011.06

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Summary of Contents for ROHS EmETXe-i9652

  • Page 1 EmETXe-i9652 COM Express CPU Module User’s Manual Version 1.2 2011.06...
  • Page 2 This page is intentionally left blank.

  • Page 3: Table Of Contents

    Index Table of Contents Chapter 1 - Introduction ..........1 1.1 Copyright Notice ............2 1.2 Declaration of Conformity ........2 1.3 About This User’s Manual ........3 1.4 Warning ..............3 1.5 Replacing the Lithium Battery .........3 1.6 Technical Support .............4 1.7 Warranty ..............4 1.8 Packing List ...............5 1.9 Ordering Information ..........5 1.10 Specifications ............6...
  • Page 4 Index 3.2.11 Remote Access Configuration .......36 3.3 Advanced PCI/PnP Settings ........37 3.4 Boot Settings ............39 3.4.1 Boot Settings Configuration ......40 3.5 Security ..............41 3.6 Advanced Chipset Settings ........43 3.6.1 North Bridge Chipset Configuration ....43 3.6.2 South Bridge Chipset Configuration ....46 3.7 Exit Options .............48 3.8 Beep Sound codes list..........53 3.8.1 Boot Block Beep Codes ........53...

  • Page 5: Chapter 1 Introduction

    Introduction Chapter 1 Introduction Chapter 1 - Introduction - 1 -...

  • Page 6: Copyright Notice

    ARBOR Technology Corp. certifies that all components in its products are in compliance and conform to the European Union’s Restriction of Use of Haz- ardous Substances in Electrical and Electronic Equipment (RoHS) Directive 2002/95/EC. The above mentioned directive was published on 2/13/2003. The main pur-...

  • Page 7: About This User's Manual

    Introduction are to enforce by 7/1/2006. ARBOR Technology Corp. hereby states that the listed products do not con- tain unintentional additions of lead, mercury, hex chrome, PBB or PBDB that exceed a maximum concentration value of 0.1% by weight or for cadmium exceed 0.01% by weight, per homogenous material.

  • Page 8: Technical Support

    Introduction 1.6 Technical Support If you have any technical difficulties, please do not hesitate to call or e-mail our customer service. http://www.arbor.com.tw E-mail:info@arbor.com.tw 1.7 Warranty This product is warranted to be in good working order for a period of two years from the date of purchase.

  • Page 9: Packing List

    Introduction 1.8 Packing List 1 x EmETXe-i9652 COM Express CPU Module 1 x Driver CD 1 x Quick Installation Guide If any of the above items is damaged or missing, contact your vendor immediately. 1.9 Ordering Information Socket P Intel® Core™ 2 Duo/Celeron® M COM...

  • Page 10: Specifications

    Introduction 1.10 Specifications Form Factor COM Express Type 2 CPU Module Intel® Core™ 2 Duo processor, up to 800MHz FSB Intel® Celeron® M processor with 533/667MHz Chipset Intel® GME965 + Intel® ICH8M 2 x 200-pin DDR2 SO-DIMM sockets supporting System Memory 533/667MHz SDRAM up to 4GB Integrated Intel®...

  • Page 11: Board Dimensions

    Introduction 1.11 Board Dimensions 43.28 DIMM2 DIMM1 CPU Socket 76.00 41.00 4.00 125.00 Unit: mm 45.35 - 7 -...
  • Page 12 Introduction This page is intentionally left blank. - 8 -...

  • Page 13: Chapter 2 Installation

    Installation Chapter 2 Installation Chapter 2 - Installation - 9 -...

  • Page 14: What Is " Com Express

    Installation 2.1 What is “ COM Express ”? With more and more demands on small and embedded industrial boards, a multi-functioned COM (Computer-on-Module) is the great one of the solutions. COM Express, board-to-board connectors consist of two rows of 220 pins each.

  • Page 15: Block Diagram

    Installation 2.2 Block Diagram Socket P Intel® Celeron® M/Core™ 2 Duo CPU 533/667/800MHz 2 x 200 pins DDRII Dual Channel DDRII SO-DIMM socket Analog Mobile Intel® R.G.B. GME965 18-24-bit LVDS PCIe*16 TV-Out AC’97 Link PCI Bus LPC I/F USB I/F IDE ATA I/F Intel®...

  • Page 16: Jumpers And Connectors

    Installation 2.3 Jumpers and Connectors DIMM2 DIMM1 CPU Socket D110 C110 B110 A110 - 12 -...

  • Page 17: Com Express Ab Connector

    Installation 2.4 COM Express AB Connector B1 GND GND A1 B2 GBE0_ACT# GBE0_MDI3- A2 B3 LPC_FRAME# GBE0_MDI3+ A3 B4 LPC_AD0 GBE0_LINK100# A4 B5 LPC_AD1 GBE0_LINK1000# A5 B6 LPC_AD2 GBE0_MDI2- A6 B7 LPC_AD3 GBE0_MDI2+ A7 B8 LPC_DRQ0# GBE0_LINK# A8 B9 LPC_DRQ1# GBE0_MDI1- A9 B10 LPC_CLK GBE0_MDI1+ A10...
  • Page 18 Installation B56 N/C N/C A56 B57 GPO2 GND A57 B58 N/C N/C A58 B59 N/C N/C A59 B60 GND GND A60 B61 PCIE_RX2+ PCIE_TX2+ A61 B62 PCIE_RX2- PCIE_TX2- A62 B63 GPO3 GPI1 A63 B64 PCIE_RX1+ PCIE_TX1+ A64 B65 PCIE_RX1- PCIE_TX1- A65 B66 WAKE0# GND A66 B67 WAKE1#...

  • Page 19: Com Express Cd Connector

    Installation 2.5 COM Express CD Connector D1 GND GND C1 D2 IDE_D5 IDE_D7 C2 D3 IDE_D10 IDE_D6 C3 D4 IDE_D11 IDE_D3 C4 D5 IDE_D12 IDE_D15 C5 D6 IDE_D4 IDE_D8 C6 D7 IDE_D0 IDE_D9 C7 D8 IDE_REQ IDE_D2 C8 D9 IDE_IOW# IDE_D13 C9 D10 IDE_ACK# IDE_D1 C10...
  • Page 20 Installation D56 PEG_TX1- PEG_RX1- C56 D57 TYPE2# TYPE1# C57 D58 PEG_TX2+ PEG_RX2+ C58 D59 PEG_TX2- PEG_RX2- C59 D60 GND GND C60 D61 PEG_TX3+ PEG_RX3+ C61 D62 PEG_TX3- PEG_RX3- C62 D63 RSVD RSVD C63 D64 RSVD RSVD C64 D65 PEG_TX4+ PEG_RX4+ C65 D66 PEG_TX4- PEG_RX4- C66 D67 GND...

  • Page 21: The Installation Paths Of Cd Driver

    Installation 2.6 The Installation Paths of CD Driver Windows 2000 & XP Driver Path CHIPSET \CHIPSET\INF 9.11 \ETHERNET\REALTEK\8111_WINXP_5764 \GRAPHICS\INTEL_2K_XP_32\1432 Windows 7 Driver Path CHIPSET \CHIPSET\INF 9.11 Windows 7 built-in LAN driver \GRAPHICS\INTEL_WIN7_32\1930 \GRAPHICS\INTEL_WIN7_64\1930 - 17 -...
  • Page 22 Installation This page is intentionally left blank. - 18 -...

  • Page 23: Chapter 3 - Bios

    BIOS Chapter 3 BIOS Chapter 3 - BIOS - 19 -...

  • Page 24: Bios Main Setup

    BIOS 3.1 BIOS Main Setup The AMI BIOS provides a setup utility program for specifying the system configurations and settings. The BIOS ROM of the system stores the setup utility. When you turn on the computer, the AMI BIOS is immediately activated. The Main displays system overview status.

  • Page 25: Advanced Settings

    BIOS System Date Set the system date. Note that the ‘Day’ automatically changes when you set the date. The date format is: Day : Sun to Sat Month : 1 to 12 Date : 1 to 31 Year : 1999 to 2099 3.2 Advanced Settings - 21 -...

  • Page 26: Cpu Configuration

    BIOS 3.2.1 CPU Configuration The CPU Configuration setup screen varies depending on the installed processor. Hardware Prefetcher This should be enabled in order to enable or disable the Hardware Prefetcher Disable Feature. Enable - Enable Hardware Prefetcher. Disabled - Disable Hardware Prefetcher. Adjacent Cache Line Prefetch This should be enabled in order to enable or disable the cache Prefetcher Disable Feature.
  • Page 27 BIOS Cache L1 & L2 CPU Internal Cache & External Cache: These two categories speed up memory access. However, it depends on CPU/chipset design. Enable - Enable cache. Disabled - Disable cache Max CPUID Value Limit Disabled for Windows XP. Vanderpool Technology Enable this item will allow a platform to run multiple virtual operating systems and applications in independent partitions.

  • Page 28: Ide Configuration

    BIOS 3.2.2 IDE Configuration Primary/Secondary/Third IDE Master/Slave Select one of the hard disk drives to configure. Press <Enter> to access its sub menu. - 24 -...

  • Page 29: Floppy Configuration

    BIOS 3.2.3 Floppy Configuration Select the type of floppy disk drive installed in your system. The choice: None 360K 5.25” 1.2M 5.25” 720K 3.5” 1.44M 3.5” 2.88M 3.5” - 25 -...

  • Page 30: Super Io Configuration

    BIOS 3.2.4 Super IO Configuration Onboard Floppy Controller Select “Enabled” if your system has a floppy disk controller (FDC) installed on the system board and you wish to use it. If you didn’t install an FDC or the system has no floppy drive, select Disabled in this field. The Choice: Enabled, Disabled Serial Port1 / Port2 Address Select an address and corresponding interrupt for the first and second serial...

  • Page 31: Parallel Port Address

    BIOS Serial Port2 Mode Allows BIOS to select mode for serial Port2. Parallel Port Address Select an address for the parallel port. The choice: Disabled Parallel Port Mode Select an operating mode for the onboard parallel port. Select Normal, Compatible or SPP unless you are certain both of your hardware and software support one of the other available modes.

  • Page 32: Hardware Health Configuration

    BIOS 3.2.5 Hardware Health Configuration System/ CPU Temperature 1 Displays the current System / CPU fan temperature. CPU / System Fan Speed Shows the current CPU / System Fan operating speed. Vcore Displays the voltage level of CPU (Vcore). +5.0V / +3.3V / +12.0V / 5Vsb / VBAT Shows the voltage level of the +3.3V, +5.0V, +12.0V, +5V standby and battery.

  • Page 33: Acpi Configuration

    BIOS 3.2.6 ACPI Configuration Suspend mode Select the ACPI state used for System Suspend. The Choice: S1 (POS) - 29 -...

  • Page 34: Ahci Configuration

    BIOS 3.2.7 AHCI Configuration AHCI Port 0 / Port 1 / Port 2 While entering setup, BIOS auto detects the presence of IDE devices. This displays the status of auto detection of IDE devices. - 30 -...

  • Page 35: Apm Configuration

    BIOS 3.2.8 APM Configuration Power Management/APM This category allows you to select the type (or degree) of power saving and is directly related to the following modes: 1. HDD Power Down 2. Doze Mode 3. Suspend Mode Video Power Down Mode This option defines the level of power-saving mode requires in to power down the video display.

  • Page 36: Power Button Mode

    BIOS Suspend Time Out Go into Suspend in the specified time. The Choice: Enabled, Disabled Keyboard & PS/2 Mouse Monitor KBC ports 60/64. Power Button Mode Pressing the power button for more than 4 seconds forces the system to enter the Soft-Off state when the system has “hang”. The Choice: Delay 4 Sec, On/Off Advanced Resume Event Controls Resume On Ring...

  • Page 37: Mps Configuration

    BIOS 3.2.9 MPS Configuration MPS Revision Select the operating system that is Multi-Processors Version Control for OS. The Choice: 1.4, 1.1. - 33 -...

  • Page 38: Usb Configuration

    BIOS 3.2.10 USB Configuration Legacy USB Support Enables support for legacy USB. AUTO option disables legacy support if no USB devices are connected. USB 2.0 Controller Mode Configures the USB 2.0 controller in High Speed (480Mbps) or Full Speed (12MBPS). BIOS EHCI Hand-Off This is a work around for OSs without EHCI hand-Off support.
  • Page 39 BIOS USB Mass Storage Reset Delay Number of seconds POST waits for the USB mass storage device after start unit command. Emulation Type If Auto, USB devices less than 530MB will be emulated as Floppy and remaining as hard drive. Forced FDD option can be used to force a HDD formatted drive to BOOT as FDD.

  • Page 40: Remote Access Configuration

    BIOS 3.2.11 Remote Access Configuration Remote Access Configure Remote Access type and parameters. The Choice: Enabled, Disabled. Serial port number Select Serial Port for console redirection. Make sure the selected port is enabled. The Choice: COM1, COM2. Base Address, IRQ Select Serial Port for console redirection.

  • Page 41: Advanced Pci/Pnp Settings

    BIOS 3.3 Advanced PCI/PnP Settings Clear NVRAM Clear NVRAM during System BOOT. The Choice: Yes, No. - 37 -...

  • Page 42: Pci Latency Timer

    BIOS Plug & Play O/S No: Lets the BIOS configure all the devices in the system. Yes: lets the operating system configure Plug and Play (PnP) devices not required for BOOT if your system has a Plug and Play operating system. PCI Latency Timer Value in units of PCI clocks for PCI device latency timer register.

  • Page 43: Boot Settings

    BIOS 3.4 Boot Settings Boot Device Priority Press Enter and it shows Bootable add-in devices. Hard Disk Drives Press Enter and it shows Bootable and Hard Disk drives. Removable Drives Press Enter and it shows Bootable and Removable drives. - 39 -...

  • Page 44: Boot Settings Configuration

    BIOS 3.4.1 Boot Settings Configuration Quick Boot Allows BIOS to skip certain tests while booting. This will decrease the time needed to boot the system. Bootup Num-Lock Set this value to allow the Number Lock setting to be modified during boot LAN Boot Function Set this option to LAN add-on Boot ROM function.

  • Page 45: Security

    BIOS 3.5 Security Auto Detect PCI Clk It enables or disables the auto detection of the PCI clock. Setting: Enabled (Default), Disabled. Supervisor Password & User Password You can set either supervisor or user password, or both of then. The differences between are: Set Supervisor Password: Can enter and change the options of the setup menus.

  • Page 46: Boot Sector Virus Protection

    BIOS Type the password, up to eight characters in length, and press <Enter>. The password typed now will clear any previously entered password from CMOS memory. You will be asked to confirm the password. Type the password again and press <Enter>. You may also press <ESC> to abort the selection and not enter a password.

  • Page 47: Advanced Chipset Settings

    BIOS 3.6 Advanced Chipset Settings 3.6.1 North Bridge Chipset Configuration Boots Graphic Adapter Priority Select which graphics controller to use as the primary boot device. Internal Graphic Mode Select Select the amount of system memory used by the Internal graphics device. - 43 -...
  • Page 48 BIOS Video Function Configuration DVMT Mode Select The Choice: FIXED, DVMT (Default), Both. DVMT/FIXED Memory The Choice: 64MB, 128MB (Default), 224MB. Boot Display The Choice: CRT + LVDS (Default). - 44 -...
  • Page 49 BIOS Flat Panel Type It allows you to select the LCD Panel type as below --- The Choice: 640x480 800x600 1024x768 18bits 1 (Default) 1280x1024 1400x1050 1400x1050 1600x1200 1280x768 1680x1050 1920x1200 TV Standard The Choice: VBIOS-Default Spread Spectrum Clock It sets the value of the spread spectrum. It is for CE testing use only. The Choice: Disabled (Default), Enabled.

  • Page 50: South Bridge Chipset Configuration

    BIOS 3.6.2 South Bridge Chipset Configuration USB Funtion This item allows you to active USB ports. The Choice: Disabled 2 USB Ports 4 USB Ports 6 USB Ports 8 USB Ports 10 USB Ports - 46 -...

  • Page 51: Onboard Lan

    BIOS USB 2.0 Controller Select “Enabled” if your system contains a Universal Serial Bus 2.0 (USB 2.0) controller and you have USB peripherals. The Choice: Enabled, Disabled. HDA Controller This item allows you to select the chipset family to support High Definition Audio Controller.

  • Page 52: Exit Options

    BIOS 3.7 Exit Options Save Changes and Exit Pressing <Enter> on this item asks for confirmation: Save configuration changes and exit setup? Pressing <OK> stores the selection made in the menus in CMOS - a special section of memory that stays on after you turn your system off. The next time you boot your computer, the BIOS configures your system according to the Setup selections stored in CMOS.

  • Page 53: Discard Changes And Exit

    BIOS Discard Changes and Exit Exit system setup without saving any changes. <ESC> key can be used for this operation. - 49 -...

  • Page 54: Discard Changes

    BIOS Discard Changes Discards changes done so far to any of the setup questions. <F7> can be used for this operation. - 50 -...

  • Page 55: Load Optimal Defaults

    BIOS Load Optimal Defaults When you press <Enter> on this item you get a confirmation dialog box with a message: Load Optimal Defaults? [OK] [Cancel] Pressing [OK] loads the BIOS Optimal Default values for all the setup questions. <F9> key can be used for this operation. - 51 -...

  • Page 56: Load Failsafe Defaults

    BIOS Load Failsafe Defaults When you press <Enter> on this item you get a confirmation dialog box with a message: Load Failsafe Defaults? [OK] [Cancel] Pressing [OK] loads the BIOS Failsafe Default values for all the setup questions. <F8> key can be used for this operation. - 52 -...

  • Page 57: Beep Sound Codes List

    BIOS 3.8 Beep Sound codes list 3.8.1 Boot Block Beep Codes Number of Beeps Description Insert diskette in floppy drive A: ‘AMIBOOT.ROM’ file not found in root directory of diskette in A: Flash Programming successful Floppy read error Keyboard controller BAT command failed No Flash EPROM detected Floppy controller failure Boot Block BIOS checksum error...

  • Page 58: Troubleshooting Post Bios Beep Codes

    BIOS 3.8.3 Troubleshooting POST BIOS Beep Codes Number of Beeps Description Reseat the memory, or replace with known good 1, 2 or 3 modules. Fatal error indicating a serious problem with the system. Consult your system manufacturer. Before declaring the motherboard beyond all hope, eliminate the possibility of interference by a malfunctioning add-in card.

  • Page 59: Ami Bios Checkpoints

    BIOS 3.9 AMI BIOS Checkpoints 3.9.1 Bootblock Initialization Code Checkpoints The Bootblock initialization code sets up the chipset, memory and other components before system memory is available. The following table describes the type of checkpoints that may occur during the bootblock initialization portion of the BIOS (Note) Checkpoint...
  • Page 60 BIOS Both key sequence and OEM specific method are checked to determine if BIOS recovery is forced. If BIOS recovery is necessary, control flows tocheckpoint E0. See Bootblock Recovery Code Checkpoints section of document for more information. Restore CPUID value back into register. The Bootblock- Runtime interface module is moved to system memory and control is given to it.

  • Page 61: Bootblock Recovery Code Checkpoints

    BIOS 3.9.2 Bootblock Recovery Code Checkpoints The Bootblock recovery code gets control when the BIOS determines that a BIOS recovery needs to occur because the user has forced the update or the BIOS checksum is corrupt. The following table describes the type of checkpoints that may occur during the Bootblock recovery portion of the BIOS (Note)
  • Page 62 BIOS Erase the flash part. Program the flash part. The flash has been updated successfully. Make flash write disabled. Disable ATAPI hardware. Restore CPUID value back into register. Give control to F000 ROM at F000:FFF0h. - 58 -...

  • Page 63: Post Code Checkpoints

    BIOS 3.9.3 POST Code Checkpoints The POST code checkpoints are the largest set of checkpoints during the BIOS pre-boot process. The following table describes the type of checkpoints that may occur during the POST portion of the BIOS (Note) Checkpoint Description Disable NMI, Parity, video for EGA, and DMA controllers.
  • Page 64 BIOS Early CPU Init Exit Initializes the 8042 compatible Key Board Controller. Detects the presence of PS/2 mouse. Detects the presence of Keyboard in KBC port. Testing and initialization of different Input Devices. Also, update the Kernel Variables. Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1.
  • Page 65 BIOS Initializes different devices through DIM. See DIM Code Checkpoints section of document for more information. USB controllers are initialized at this point. Initializes DMAC-1 & DMAC-2. Initialize RTC date/time. Test for total memory installed in the system. Also, Check for DEL or ESC keys to limit memory test.
  • Page 66 BIOS Takes care of runtime image preparation for different BIOS modules. Fill the free area in F000h segment with 0FFh. Initializes the Microsoft IRQ Routing Table. Prepares the runtime language module. Disables the system configuration display if needed. Initialize runtime language module. Display boot option popup menu.

  • Page 67: Dim Code Checkpoints

    BIOS 3.9.4 DIM Code Checkpoints The Device Initialization Manager (DIM) gets control at various times during BIOS POST to initialize different system busses. The following table describes the main checkpoints where the DIM module is accessed (Note) Checkpoint Description Initialize different buses and perform the following functions: Reset, Detect, and Disable (function 0);...
  • Page 68 BIOS While control is in the different functions, additional checkpoints are output to port 80h as a word value to identify the routines under execution. The low byte value indicates the main POST Code Checkpoint. The high byte is divided into two nibbles and contains two fields. The details of the high byte of these checkpoints are as follows: HIGH BYTE XY The upper nibble “X”...

  • Page 69: Acpi Runtime Checkpoints

    BIOS 3.9.5 ACPI Runtime Checkpoints ACPI checkpoints are displayed when an ACPI capable operating system either enters or leaves a sleep state. The following table describes the type of checkpoints that may occur during ACPI sleep or wake events (Note) Checkpoint Description First ASL check point.
  • Page 70 BIOS This page is intentionally left blank. - 66 -...

  • Page 71: Appendix

    Appendix Appendix Appendix - 67 -...

  • Page 72: Appendix A: I/O Port Address Map

    Appendix Appendix A: I/O Port Address Map Each peripheral device in the system is assigned a set of I/O port addresses which also becomes the identity of the device. The following table lists the I/O port addresses used. 0000h - 0000Fh DMA Controller 0080h - 009Fh DMA Controller...

  • Page 73: Appendix B: Bios Memory Map

    Appendix 0A10h-0A17h Hardware Monitor 0CF8h PCI Configuration address 0CFCh PCI Configuration Data Appendix B: BIOS Memory Map Item Address Description 00000h-9FFFFh DOS Kernel Area A0000h,BFFFFh EGA and VGA Video Buffer (128KB) C0000h-CFFFFh EGA/VGA ROM D0000h-DFFFFh Adaptor ROM E0000h-FFFFFh System BIOS - 69 -...

  • Page 74: Appendix C: Interrupt Request Lines (Irq)

    Appendix Appendix C: Interrupt Request Lines (IRQ) Peripheral devices use interrupt request lines to notify CPU for the service required. The following table shows the IRQ used by the devices on board. Level Function IRQ 00 System Timer IRQ 01 Standard 101/102-Key or Microsoft Natural PS/2 Keyboard IRQ 02 VGA and Link to Secondary PIC...

  • Page 75: Appendix D: Digital I/O Setting

    Appendix Appendix D: Digital I/O Setting Below are the source codes written in assembly & C, please take them for Digital I/O application examples. The default I/O address is 6Eh. Assembly Code ax,402h dx,ax al,00h dx,al ; clear i2c bus ax,400h dx,ax al,0ffh...
  • Page 76 Appendix ax,400h dx,ax al,0ffh dx,ax ; clear i2c bus status ax,404h dx,ax al,06eh dx,ax ; Set I2C Device Address=6eh ax,403h dx,ax al,020h dx,ax ;select GPIO 2 (index=20h) ax,405h dx,ax al,0ffh dx,ax ;Set all GPIO 2 pin as output ax,402h dx,ax al,048h dx,ax ;start write, active...
  • Page 77 Appendix ax,405h dx,ax al,0ffh dx,ax ;Set all GPIO 1 data = high ax,402h dx,ax al,048h dx,ax ;start write, active ;------------------------------------------------------------- ax,402h dx,ax al,00h dx,al ; clear i2c bus ax,400h dx,ax al,0ffh dx,ax ; clear i2c bus status ax,404h dx,ax al,06eh dx,ax ;...
  • Page 78 Appendix C Language Code /*----- Include Header Area -----*/ #include "math.h" #include "stdio.h" #include "dos.h" /*----- routing, sub-routing -----*/ void main(int argc, char *argv[]) int SMB_PORT_AD = 0x400; int SMB_DEVICE_ADD = 0x6e; /*75111R's Add=6eh */ int i,j; Index x0, GPIO1x Output pin control, Set all pin as output SMB_Byte_WRITE(SMB_PORT_AD,SMB_DEVICE_ADD,0x10,0xff);...
  • Page 79 Appendix SMB_Byte_WRITE(int SMPORT, int DeviceID, int REG_INDEX, int REG_DATA) outportb(SMPORT+02, 0x00); /* clear */ outportb(SMPORT+00, 0xff); /* clear */ delay(10); outportb(SMPORT+04, DeviceID); /* I2C Device Address */ outportb(SMPORT+03, REG_INDEX); /* Register Address in device */ outportb(SMPORT+05, REG_DATA); /* Data Value */ outportb(SMPORT+02, 0x48);...
  • Page 80 Appendix This page is intentionally left blank. - 76 -...

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