Cpu 4/7 (Power - Clevo E5120Q Service Manual

CPU 4/7 (Power)

P ROCES SOR
U 1 6F
PRO CESSOR CORE POWER
V C O R E
48A
A G 3 5
V C C 1
A G 3 4
I CC M AX M a xi m um P r oc es s or SV 4 8
V C C 2
A G 3 3
V C C 3
A G 3 2
A G 3 1 V C C 4
V C C 5
V C O R E A G 3 0
V C C 6
A G 2 9
A G 2 8 V C C 7
C 3 2 3 C 3 3 1 C 3 3 5 C 3 3 7
V C C 8
A G 2 7
V C C 9
A G 2 6
V C C 1 0
A F 3 5
A F 3 4 V C C 1 1
V C C 1 2
A F 3 3
V C C 1 3
A F 3 2
V C C 1 4
A F 3 1
A F 3 0 V C C 1 5
V C C 1 6
A F 2 9
V C C 1 7
A F 2 8
A F 2 7 V C C 1 8
V C C 1 9
A F 2 6
V C C 2 0
A D 3 5
V C C 2 1
C 3 4 2 C 3 5 2 C 3 2 9 C 3 1 8 A D 3 4
A D 3 3 V C C 2 2
V C C 2 3
A D 3 2
V C C 2 4
A D 3 1
V C C 2 5
A D 3 0
A D 2 9 V C C 2 6
V C C 2 7
A D 2 8
V C C 2 8
A D 2 7
V C C 2 9
A D 2 6
V C C 3 0
A C 3 5
V C C 3 1
A C 3 4
V C C 3 2
A C 3 3
A C 3 2 V C C 3 3
V C C 3 4
A C 3 1
V C C 3 5
A C 3 0
C 3 3 2 C 3 5 6 C 3 5 5 C 3 5 4
V C C 3 6
A C 2 9
A C 2 8 V C C 3 7
V C C 3 8
A C 2 7
V C C 3 9
A C 2 6
V C C 4 0
A A 3 5
A A 3 4 V C C 4 1
V C C 4 2
A A 3 3
V C C 4 3
A A 3 2
A A 3 1 V C C 4 4
V C C 4 5
A A 3 0
V C C 4 6
A A 2 9
V C C 4 7
A A 2 8
A A 2 7 V C C 4 8
V C C 4 9
A A 2 6
V C C 5 0
Y 3 5
V C C 5 1
Y 3 4
Y 3 3 V C C 5 2
V C C 5 3
V C O R E Y 3 2
V C C 5 4
Y 3 1
Y 3 0 V C C 5 5
V C C 5 6
Y 2 9
C 3 4 8 C 3 4 6 C 3 4 5 C 3 4 4
V C C 5 7
Y 2 8
V C C 5 8
Y 2 7
Y 2 6 V C C 5 9
V C C 6 0
V 3 5
V C C 6 1
V 3 4
V C C 6 2
V 3 3
V 3 2 V C C 6 3
V C C 6 4
V 3 1
V C C 6 5
V 3 0
V 2 9 V C C 6 6
V C C 6 7
V 2 8
V C C 6 8
V 2 7
V C C 6 9
V 2 6
U 3 5 V C C 7 0
C 3 2 6 C 3 2 5 C 3 2 7 C 3 4 7
V C C 7 1
U 3 4
V C C 7 2
U 3 3
V C C 7 3
U 3 2
U 3 1 V C C 7 4
V C C 7 5
U 3 0
V C C 7 6
U 2 9
V C C 7 7
U 2 8
V C C 7 8
U 2 7
V C C 7 9
U 2 6
V C C 8 0
R 3 5
R 3 4 V C C 8 1
V C C 8 2
R 3 3
V C C 8 3
R 3 2
V C C 8 4
C 3 4 0 C 3 3 9 C 3 3 8 C 3 3 3 R 3 1
R 3 0 V C C 8 5
V C C 8 6
R 2 9
V C C 8 7
R 2 8
V C C 8 8
R 2 7
R 2 6 V C C 8 9
V C C 9 0
P 3 5
V C C 9 1
P 3 4
P 3 3 V C C 9 2
V C C 9 3
P 3 2
V C C 9 4
P 3 1
V C C 9 5
P 3 0
P 2 9 V C C 9 6
V C C 9 7
P 2 8
V C C 9 8
P 2 7
V C C 9 9
P 2 6
V C C 1 0 0
P Z 98 9 2 7 -3 6 4 1- 01 F
4/7 ( PO WER )
PROCESS OR UNCORE POWER
A H 1 4
V T T 0 _ 1
A H 1 2
V T T 0 _ 2
A H 1 1
C 2 9 C 3 0 C 3 24
V T T 0 _ 3
A H 1 0
V T T 0 _ 4 J 1 4
1 0 u _ 6. 3V _X 5 R _ 0 6 *1 0 u _ 6. 3V _ X5 R _ 0 6 1 0 u _ 6. 3V _ X5 R _ 0 6
V T T 0 _ 5
J 1 3
V T T 0 _ 6
H 1 4
V T T 0 _ 7 H 1 2
V T T 0 _ 8
G 1 4
V T T 0 _ 9
G 1 3
V TT 0 _ 1 0
G 1 2
V TT 0 _ 1 1 G 1 1
V TT 0 _ 1 2
F 14
C 3 6 C 3 0 3 C 3 4
V TT 0 _ 1 3
F 13
V TT 0 _ 1 4
F 12 1 0 u _ 6. 3V _X 5 R _ 0 6 1 0 u _ 6 . 3 V _ X 5R _ 0 6 10 u _ 6 . 3 V _ X 5 R _ 0 6
V TT 0 _ 1 5 F 11
V TT 0 _ 1 6
E 14
V TT 0 _ 1 7
E 12
V TT 0 _ 1 8 D 1 4
V TT 0 _ 1 9
D 1 3
V TT 0 _ 2 0
D 1 2
V TT 0 _ 2 1
D 1 1
V TT 0 _ 2 2 C 1 4
V TT 0 _ 2 3
C 1 3
V TT 0 _ 2 4
C 1 2
V TT 0 _ 2 5
C 1 1
V TT 0 _ 2 6 B 14
V TT 0 _ 2 7
B 12
V TT 0 _ 2 8
A 14
V TT 0 _ 2 9
A 13
V TT 0 _ 3 0
A 12
V TT 0 _ 3 1
A 11
V TT 0 _ 3 2
A F 1 0
V TT 0 _ 3 3
A E 1 0
V TT 0 _ 3 4 A C 1 0
C 3 0 4 C 3 0 5
V TT 0 _ 3 5
A B 1 0
V TT 0 _ 3 6
Y 1 0
2 2 u _ 6 . 3 V _ X 5R _ 0 8 22 u _ 6 . 3 V _ X 5 R _ 0 8
V TT 0 _ 3 7
W 10
V TT 0 _ 3 8 U 1 0
V TT 0 _ 3 9
T 1 0
V TT 0 _ 4 0
J 1 2
V TT 0 _ 4 1 J 1 1
V TT 0 _ 4 2
J 1 6
+ V T T_ 4 3 R 2 1 6 *1 5 m i l _ s h o rt _ 0 6
V TT 0 _ 4 3
J 1 5 + V T T_ 4 4
R 2 1 5 *1 5 m i l _ s h o rt _ 0 6
V TT 0 _ 4 4
1 . 1 V S _ V T T
1K PU t o V TT an d 1 K P D to GN D
fo r P OC
R 2 25
VC ORE * 1 K _ 1% _ 0 4
A N 3 3 P S I #
P S I #
A K 3 5
R 2 26
V I D [ 0 ] H _V I D 0 3 6
A K 3 3
V I D [ 1 ] H _V I D 1 3 6
A K 3 4 1 K _ 1 % _ 0 4
H _V I D 2 3 6
V I D [ 2 ] A L3 5
V I D [ 3 ] H _V I D 3 3 6
A L3 3
V I D [ 4 ] H _V I D 4 3 6
A M3 3
V I D [ 5 ] H _V I D 5 3 6
A M3 5
H _V I D 6 3 6
V I D [ 6 ] A M3 4
P R O C _ D P R S L P V R
G 1 5
H _ V T TV I D 1
V T T _ S E L E C T
TO V CORE POW ER CONT ROL
A N 3 5
I M O N 3 6
I S E N S E
A J3 4
V C C _ S E N S E 3 6
V C C _ S E N S E
A J3 5
V S S _ S E N S E 36
V S S _ S E N S E
B 15
V T T _ S E N S E 3 4
V T T_ S E N S E A 15
V S S _S E N S E _ V T T
1 . 1 V S _ V TT
V TT TOTAL 2 1A
C 3 5 C 33 C 3 0 1 C 3 3 4
*1 0 u _ 6. 3V _ X5 R _ 0 6 *1 0 u _ 6 . 3 V _ X 5 R _ 0 6 2 2 u _ 6 . 3V _ X5 R _ 0 8 2 2 u _ 6 . 3 V _ X 5 R _ 0 8
C 3 2 8 IC CM AX_ VT T M ax Cu rre nt
fo r VTT R ail
*1 0 u _ 6 . 3 V _ X 5R _ 0 6
SV 18
The decoupling capacitors, filter
recommendations and sense resistors on the
CPU/PCH Rails are specific to the CRB
Implementation. Customers need to follow the
recommendations in the Calpella Platform
1. 1V S _ V T T
Design Guide
C 3 1 2
2 2 u_ 6 . 3 V _ X 5 R _0 8
1.1VS_VTT
Please note that the
VTT Rail Values are
Auburndale VTT=1.05V
P S I # 3 6
1 . 1 V S _ V T T
R 2 2 3
1 K _ 1 % _0 4
P M _ D P R S LP V R 3 6
R 2 2 2
*1 K _ 1 % _ 0 4
V C O R E 3 6
1 . 1V S _ V T T 2 , 4 , 7 , 1 4 , 1 5 , 1 6, 1 9 , 2 0 , 2 1 , 3 4 , 3 5 , 3 6
Schematic Diagrams
Sheet 6 of 42
CPU 4/7
(Power)
CPU 4/7 (Power) B - 7