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Schematic Diagrams
CPU 4/7 (Power)
PROCES SOR CORE POWER
ICCMAX Maximum Proces sor
Sheet 5 of 43
CPU 4/7
(Power)
B - 6 CPU 4/7 (Power)
Sandy Bridge Processor 4/7
U 3 4 F
V C O R E
48A
A G3 5
V C C 1
A G3 4
V C C 2
A G3 3
V C C 3
A G3 2
SV 48
V C C 4
A G3 1
A G3 0
V C C 5
V C C 6
V C OR E
A G2 9
V C C 7
A G2 8
A G2 7
V C C 8
C 3 5 3
2 2u _ 6 . 3 V _ X 5 R _ 0 8
V C C 9
A G2 6
V C C 1 0
A F 3 5
C 3 7 1
2 2u _ 6 . 3 V _ X 5 R _ 0 8
V C C 1 1
A F 3 4
V C C 1 2
A F 3 3
C 3 6 6
2 2u _ 6 . 3 V _ X 5 R _ 0 8
V C C 1 3
A F 3 2
V C C 1 4
C 3 5 4
2 2u _ 6 . 3 V _ X 5 R _ 0 8
A F 3 1
A F 3 0
V C C 1 5
V C C 1 6
A F 2 9
C 3 5 9
2 2u _ 6 . 3 V _ X 5 R _ 0 8
V C C 1 7
A F 2 8
A F 2 7
V C C 1 8
C 3 6 3
2 2u _ 6 . 3 V _ X 5 R _ 0 8
V C C 1 9
A F 2 6
V C C 2 0
A D 3 5
C 3 3 7
2 2u _ 6 . 3 V _ X 5 R _ 0 8
V C C 2 1
A D 3 4
A D 3 3
V C C 2 2
C 3 3 2
2 2u _ 6 . 3 V _ X 5 R _ 0 8
V C C 2 3
A D 3 2
V C C 2 4
C 3 5 1
2 2u _ 6 . 3 V _ X 5 R _ 0 8
A D 3 1
A D 3 0
V C C 2 5
V C C 2 6
A D 2 9
C 3 3 6
2 2u _ 6 . 3 V _ X 5 R _ 0 8
V C C 2 7
A D 2 8
A D 2 7
V C C 2 8
V C C 2 9
A D 2 6
V C C 3 0
A C 3 5
V C C 3 1
V C OR E
A C 3 4
A C 3 3
V C C 3 2
V C C 3 3
A C 3 2
C 6 9
1 0u _ 6 . 3 V _ X 5 R _ 0 6
V C C 3 4
A C 3 1
A C 3 0
V C C 3 5
C 3 3
1 0u _ 6 . 3 V _ X 5 R _ 0 6
V C C 3 6
A C 2 9
V C C 3 7
A C 2 8
C 7 4
1 0u _ 6 . 3 V _ X 5 R _ 0 6
V C C 3 8
A C 2 7
V C C 3 9
A C 2 6
C 5 6
1 0u _ 6 . 3 V _ X 5 R _ 0 6
V C C 4 0
A A 3 5
V C C 4 1
C 3 4
1 0u _ 6 . 3 V _ X 5 R _ 0 6
A A 3 4
A A 3 3
V C C 4 2
V C C 4 3
A A 3 2
C 5 3
1 0u _ 6 . 3 V _ X 5 R _ 0 6
V C C 4 4
A A 3 1
A A 3 0
V C C 4 5
V C C 4 6
A A 2 9
V C C 4 7
V C OR E
A A 2 8
V C C 4 8
A A 2 7
V C C 4 9
A A 2 6
C 3 6 2
*2 2 u _ 6. 3V _X 5 R _ 08
V C C 5 0
Y 3 5
V C C 5 1
C 3 6 0
*2 2 u _ 6. 3V _X 5 R _ 08
Y 3 4
Y 3 3
V C C 5 2
V C C 5 3
Y 3 2
C 3 3 4
*2 2 u _ 6. 3V _X 5 R _ 08
V C C 5 4
Y 3 1
Y 3 0
V C C 5 5
C 3 3 3
*2 2 u _ 6. 3V _X 5 R _ 08
V C C 5 6
Y 2 9
V C C 5 7
Y 2 8
C 3 5 6
*2 2 u _ 6. 3V _X 5 R _ 08
V C C 5 8
Y 2 7
Y 2 6
V C C 5 9
C 6 2
*1 0 u _ 6. 3V _X 5 R _ 06
V C C 6 0
V 3 5
V C C 6 1
C 7 2
*1 0 u _ 6. 3V _X 5 R _ 06
V 3 4
V 3 3
V C C 6 2
V C C 6 3
V 3 2
C 5 9
*1 0 u _ 6. 3V _X 5 R _ 06
V C C 6 4
V 3 1
V 3 0
V C C 6 5
C 6 6
*1 0 u _ 6. 3V _X 5 R _ 06
V C C 6 6
V 2 9
V C C 6 7
V 2 8
V C C 6 8
V 2 7
V 2 6
V C C 6 9
V C C 7 0
U 3 5
V C C 7 1
U 3 4
U 3 3
V C C 7 2
V C C 7 3
U 3 2
V C C 7 4
U 3 1
V C C 7 5
U 3 0
V C C 7 6
U 2 9
V C C 7 7
U 2 8
V C C 7 8
U 2 7
U 2 6
V C C 7 9
V C C 8 0
R 3 5
V C C 8 1
R 3 4
R 3 3
V C C 8 2
V C C 8 3
R 3 2
V C C 8 4
R 3 1
V C C 8 5
R 3 0
V C C 8 6
R 2 9
V C C 8 7
R 2 8
V C C 8 8
R 2 7
R 2 6
V C C 8 9
V C C 9 0
P 3 5
V C C 9 1
P 3 4
P 3 3
V C C 9 2
V C C 9 3
P 3 2
V C C 9 4
P 3 1
V C C 9 5
P 3 0
P 2 9
V C C 9 6
V C C 9 7
P 2 8
V C C 9 8
P 2 7
P 2 6
V C C 9 9
V C C 1 00
P Z 9 88 2 7 -3 6 4 B -0 1 F
POWER
PROCESSOR UNCORE POWER
A H 13
V C C I O 1
A H 10
V C C I O 2
A G 10
C 3 6 1
C 3 5 7
V C C I O 3
A C 10
V C C I O 4
Y 1 0
22 u _ 6 . 3 V _ X 5 R _ 0 8
22 u _ 6 . 3 V _ X 5R _ 0 8
V C C I O 5
U 1 0
V C C I O 6
P 1 0
V C C I O 7
L 1 0
V C C I O 8
J 1 4
V C C I O 9
J 1 3
C 3 5 5
C 3 4 4
V C C I O 1 0
J 1 2
V C C I O 1 1
J 1 1
*2 2 u _6 . 3 V _ X 5 R _0 8
*2 2 u _6 . 3 V _ X 5 R _0 8
V C C I O 1 2
H 1 4
V C C I O 1 3
H 1 2
V C C I O 1 4
H 1 1
V C C I O 1 5
G1 4
V C C I O 1 6
G1 3
C 3 9 6
C 4 1 9
V C C I O 1 7
G1 2
V C C I O 1 8
F 1 4
*2 2 u _6 . 3 V _ X 5 R _0 8
*2 2 u _6 . 3 V _ X 5 R _0 8
V C C I O 1 9
F 1 3
V C C I O 2 0
F 1 2
V C C I O 2 1
F 1 1
V C C I O 2 2
E 1 4
V C C I O 2 3
E 1 2
C 3 2 1
C 4 1 8
V C C I O 2 4
E 1 1
*2 2 u _6 . 3 V _ X 5 R _0 8
*2 2 u _6 . 3 V _ X 5 R _0 8
V C C I O 2 5
D 1 4
V C C I O 2 6
D 1 3
V C C I O 2 7
D 1 2
V C C I O 2 8
D 1 1
V C C I O 2 9
C 1 4
C 4 0 7
C 3 7 2
V C C I O 3 0
C 1 3
V C C I O 3 1
C 1 2
*2 2 u _6 . 3 V _ X 5 R _0 8
22 u _ 6 . 3 V _ X 5R _ 0 8
V C C I O 3 2
C 1 1
V C C I O 3 3
B 1 4
V C C I O 3 4
B 1 2
V C C I O 3 5
A 1 4
V C C I O 3 6
A 1 3
C 3 8 1
C 3 9 4
V C C I O 3 7
A 1 2
V C C I O 3 8
A 1 1
*2 2 u _6 . 3 V _ X 5 R _0 8
*2 2 u _6 . 3 V _ X 5 R _0 8
V C C I O 3 9
J 2 3
+ V 1 . 0 5 S _ V C C P _ F
R 62
* 2 0m i l _ 0 4
V C C I O 4 0
CAD Note: H_CPU_SVIDALRT#_R,H_CPU_SVIDDAT_R
Place the PU resistors close to CPU
A J 2 9
H _ C P U _ S V I D A L R T # _R
R 40 6
4 3 _ 1 % _0 4
V I D A L E R T #
A J 3 0
H _ C P U _ S V I D C L K _ R
R 88
0 _ 0 4
V I D S C L K
A J 2 8
H _ C P U _ S V I D D A T _ R
R 85
0 _ 0 4
V I D S O U T
1 . 0 5 V S _ V T T
A J 3 5
V C C _ S E N S E
A J 3 4
R 3 79
V S S _ S E N S E
1 0 _ 0 4
B 1 0
V C C I O _ S E N S E _ R
R 3 84
V C C I O_ S E N S E
A 1 0
V S S I O_ S E N S E
V S S I O_ S E N S E
R 3 83
1 0 _ 0 4
1 . 0 5 V S _ V T T
8.5A
C 3 6 5
C 3 9 8
C 3 5 0
C 4 0 2
+
2 2 u _ 6 . 3 V _ X 5R _ 0 8
* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8
* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8
22 0 u _ 6 . 3 V _ 6 . 3 *6 . 3 *4 . 2
C 3 6 4
C 3 5 8
C 3 4 6
C 4 1 7
+
* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8
* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8
2 2 u _ 6 . 3 V _ X5 R _ 0 8
22 0 u _ 6 . 3 V _ 6 . 3 *6 . 3 *4 . 2
C 4 0 6
C 3 9 7
C 3 8 4
* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8
* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8
2 2 u _ 6 . 3 V _ X5 R _ 0 8
C 3 7 5
C 3 8 3
C 3 8 2
2 2 u _ 6 . 3 V _ X 5R _ 0 8
2 2 u _ 6 . 3 V _ X 5R _ 0 8
* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8
C 3 5 2
C 3 6 7
C 3 8 5
2 2 u _ 6 . 3 V _ X 5R _ 0 8
2 2 u _ 6 . 3 V _ X 5R _ 0 8
2 2 u _ 6 . 3 V _ X5 R _ 0 8
C 4 2 0
C 3 6 8
* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8
* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8
1 . 0 5 V S _ V T T
SVID Signals
H _ C P U _S V I D A L R T #
R 4 0 8
7 5_ 1 % _ 0 4
H _C P U _ S V I D A L R T # [ 3 6 ]
H _ C P U _S V I D C L K
R 8 9
*5 4 . 9 _ 1 % _0 4
H _C P U _ S V I D C L K
[ 3 6]
H _ C P U _S V I D D A T _ R
R 8 6
1 30 _ 1 % _ 0 4
H _C P U _ S V I D D A T [ 3 6]
CAD Note: H_CPU_SVIDCLK_R
Place the PU
resistors close to VR
V C OR E _ V C C _ S E N S E
[ 3 6 ]
V C OR E _ V S S _ S E N S E [ 3 6 ]
*0 _ 0 4
V C C I O _ S E N S E
[ 34 ]
[ 3 6 , 37 ]
V C O R E
[ 2, 3 , 1 8 , 1 9 , 2 0 , 3 4 , 36 ]
1. 05 V S _ V T T
1 . 0 5 V S _ V T T
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