SOLTEK SL-65FVB User Manual page 31

Bank 0/1 2/3 4/5 DRAM
SDRAM Cycle Length
Read Around Write DRAM optimization feature: If a memory read is ad-
Concurrent PCI / HOST When disabled, CPU bus will be occupied during the
System BIOS
Cacheable
Video RAM Cacheable Choose Enabled or Disabled (default). When enabled,
AGP Aperture Size
This item allows you to select the value in this field,
Timing depending on whether the board has paged DRAMs
or EDO (Extended Data Output) DRAMs.
The choice: EDO 50ns,
You can select CAS latency time in HCLKs of 2/2 or
TIme 3/3. The system board designer should have set the
values in this field, depending on the DRAM installed.
Do not change the values in this field unless you
change specifications of the installed DRAM or the
installed CPU.
dressed to a location whose latest write isw being
held in a buffer before being written to memory, the
read is satisfied through the buffer contents, and the
read is not sent to the DRAM.
The choice: Enabled, Disabled.
entire PCI operation period.
The choice: Enabled, Disabled.
Choose Enabled or Disabled (default). When enabled,
the access to the system BIOS ROM addressed at
F0000H - FFFFFH is cached.
the access to the VGA RAM addressed is cached.
Choose 4, 8, 16, 32, 64 (default), 128 or 256 MB.
(MB) Memory mapped and graphics data structures can
reside in a Graphics Aperture. This area is like a lin-
ear buffer. BIOS will automatically report the starting
address of this buffer to the O.S.
EDO 60ns,
Slow,
Medium,
Fast,
Turbo.
65FVB/65FVB-X
31