Yamaha M7CL-32 Service Manual page 54

M7CL-32/M7CL-48
HD6417727F160CV (X2890B00) CPU
PIN
NAME I/O
NO.
1 Vcc-RTC - Power supply for RTC (1.9 V)
2 XTAL2 -
Not in use (XTAL for internal RTC)
3 EXTAL2 -
4 Vss-RTC - Power supply for RTC (0 V)
5 MD1 -
Clock mode setting
6 MD2 -
7 NMI - Not in use (Non-maskable interrupt request)
8 IRQ0/PTH[0] I
9 IRQ1/PTH[1] I
10 IRQ2/PTH[2] I External interrupt request
11 IRQ3/PTH[3] I
12 IRQ4/PTH[4] I
13 VEPWC O VEE control pin for LCD panel
14 VCPWC - VCC control pin for LCD panel
15 MD5 - Big endian setting
16 BREQ - Not in use (bus request)
17 BACK - Bus acknowledge
18 VssQ - VssQ
19 CKIO2 - System clock output
20 VccQ - VccQ
21 D31/PTB[7] I/O
22 D30/PTB[6] I/O
23 D29/PTB[5] I/O
24 D28/PTB[4] I/O
Data bus
25 D27/PTB[3] I/O
26 D26/PTB[2] I/O
27 D25/PTB[1] I/O
28 D24/PTB[0] I/O
29 VssQ - VssQ
30 D23/PTA[7] I/O Data bus
31 VccQ - VccQ
32 D22/PTA[6] I/O
33 D21/PTA[5] I/O Data bus
34 D20/PTA[4] I/O
35 Vss - Vss
36 D19/PTA[3] I/O Data bus
37 Vcc - Vcc
38 D18/PTA[2] I/O
39 D17/PTA[1] I/O Data bus
40 D16/PTA[0] I/O
41 D15 - Data bus
42 VssQ - VssQ
43 D14 - Data bus
44 VccQ - VccQ
45 D13 -
46 D12 -
47 D11 -
48 D10 -
Data bus
49 D9 -
50 D8 -
51 D7 -
52 D6 -
53 VssQ - VssQ
54 D5 - Data bus
55 VccQ - VccQ
56 D4 -
57 D3 -
58 D2 - Data bus
59 D1 -
60 D0 -
61 A0 -
62 A1 - Address bus
63 A2 -
64 VssQ - VssQ
65 A3 - Address bus
66 VccQ - VccQ
67 A4 -
68 A5 -
69 A6 -
70 A7 -
Address bus
71 A8 -
72 A9 -
73 A10 -
74 A11 -
75 VssQ - VssQ
76 A12 - Address bus
77 VccQ - VccQ
78 A13 -
79 A14 -
80 A15 -
81 A16 -
Address bus
82 A17 -
83 A18 -
84 A19 -
85 A20 -
86 VssQ - VssQ
87 A21 - Address bus
88 VccQ - VccQ
89 A22 -
Address bus
90 A23 -
91 Vss - Vss
92 A24 - Address bus
93 Vcc - Vcc
94 A25 - Address bus
95 BS O Not connected (bus cycle start signal)
96 RD - Read strobe
97 WE0/DQMLL O Write 0 signal
98 WE1/DQMLU/WE O Write 1 signal
99 WE2/DQMUL O Write 2 signal
100 VssQ - VssQ
101 WE3/DQMUU O Write 3 signal
102 VccQ - VccQ
103 RD/WR O Read/Write
104 PTE[7] O I/O
105 CS0 - Chip Select 0
106 CS2 - Chip Select 2
107 CS3 - Chip Select 3
108 CS4 O Chip Select 4
109 CS5 O Chip Select 5
110 CS6 O Chip Select 6
111 PTE[4] O Output port (SWP50 Reset)
112 PTE[5] O Output port (PLG Board Reset)
113 PTK[0] O SPD DATA
114 PTK[1] O SPD CL
115 VssQ - VssQ
116 AFE_SCLK I Not in use (USB1 D+ transmission)
117 VccQ - VccQ
118 PTM[7]/PTINT[7] I
119 PTM[6]/PTINT[6] I Not in use
120 PTM[5]/PTINT[5] I
54
PIN
FUNCTION
NO.
NAME I/O
121 PTM[4]/PINT[4] I
Not in use
122 Reserved O
123 USB1_ovr_crnt/USBF_VBUS I USB function VBUS
124 USB2_ovr_crnt_ - USB2_HOST2 over current detection
125 RTS2 O Not in use
126 PTE[2]/USB1_pwr_en O USB1 voltage control
127 PTE[1]/USB2_pwr_en O USB2 voltage control
128 CKE O Enable (SDRAM)
129 RAS for SDRAM
RAS3 O
130 PTJ[1] O Not in use
131 CAS O CAS for SDRAM
132 VssQ - VssQ
133 PTJ[3] O Output port (DAC Reset)
134 VccQ - VccQ
135 PTJ[4] O Output port (SIO Reset)
136 PTJ[5] O Output port (DAC Mute)
137 Vss - Vss
138 PTD[5]/CL1 O LCD line clock
139 Vcc - Vcc
140 PTD[7]/DON O LCD DISPLAY ON
141 PTE[6]/M_DISP O LCD alternater
142 PTE[3]/FLM O LCD frame line marker
143 TDO O JTAG (test data output)
144 DRACK0 O DMA request acceptance
145 DACK0 O DMA acknowledge
146 WAIT - Hardware wait request
147 RESETM - Manual reset request
148 PTH[5] I Analog A/D trigger
149 PTG[7] I
150 ASEMD0 -
151 ASEBRKAK Not in use
152 PTG[4] I
153 PTG[3] I
154 PTG[2] I
155 Vss - Vss
156 PTG[1] I Not in use
157 Vcc - Vcc
158 PTG[0] I Not in use
159 VssQ - VssQ
160 TRST I Not in use
161 VccQ - VccQ
162 TMS I
163 TDI I
164 TCK I
165 PTF[3]/PINT[11] I Not in use
166 PTF[2] I
167 PTF[1] I
168 PTF[0] I
169 MD0 - Clock mode setting
170 Vcc-PLL1 - Power supply for Vcc_PLL1 - PLL1(1.9 V)
171 CAP1 - External capacitance for CAP1 _ PLL1
172 Vss-PLL1 - Power supply for Vss_PLL1 _ PLL1(0 V)
173 Vss-PLL2 - Power supply for Vss_PLL2 _ PLL2 (0 V)
174 CAP2 - External capacitance for CAP2 _ PLL2
175 Vcc-PLL2 - Power supply for Vcc_PLL2 _ PLL2 (1.9 V)
176 PTH[6] I Not in use
177 Vss - Vss
178 Vcc - Vcc
179 XTAL - Clock oscillator
180 EXTAL - External clock
181 LCD15/PTM[3]/PINT[10] I
182 LCD14/PTM[2]/PINT[9] I Not in use
183 LCD13/PTM[1]/PINT[8] I
184 LCD12/PTM[0] I Input port (Flash ROM RY/BY)
185 PTJ[6] O Output port (Flash ROM write protect)
186 PTJ[7] O Output port (Flash ROM ACC)
187 CL2/PTH[7] O LCD clock output
188 VssQ - VssQ
189 CKIO - System clock input/output (for SDRAM)
190 VccQ - VccQ
191 TxD0/SCPT[0] O Output port for SCI
192 SCK0/SCPT[1] O
193 TxD_SIO/SCPT[2] O Not in use
194 SIOMCLK/SCPT[3] O
195 TxD2/SCPT[4] O Output port for SCI
196 SCK_SIO/SCPT[5] O
Not in use
197 SIOFSYNC/SCPT[6] O
198 RxD0/SCPT[0] I Receiving data 0
199 RxD_SIO/SCPT[2] I Not in use
200 Vss - Vss
201 RxD2/SCPT[4] I Receiving data 2
202 Vcc - Vcc
203 SCPT[7]IRQ5 I Not in use
204 LCD11/PTC[7]/PINT[3] O Output port (PLG CLOCK ON/OFF)
205 LCD10/PTC[6]/PINT[2] O
Not in use
206 LCD9/PTC[5]/PINT[1] O
207 VssQ - VssQ
208 LCD8/PTC[4]/PINT[0] O Not in use
209 VccQ - VccQ
210 LCD7/PTD[3] O LCD DATA7
211 LCD6/PTD[2] O LCD DATA6
212 LCD5/PTC[3] O LCD DATA5
213 LCD4/PTC[2] O LCD DATA4
214 LCD3/PTC[1] O LCD DATA3
215 LCD2/PTC[0] O LCD DATA2
216 LCD1/PTD[1] O LCD DATA1
217 LCD0/PTD[0] O LCD DATA0
218 DREQ0/PTD[4] I DMA request
219 UCLK I USB clock
220 RESETP - Power on reset request
221 CA - Hardware standby request
222 MD3 - Bus width setting for area0
223 MD4 -
224 Scan_testen - Test pin (fixed to 3.3 V)
225 Avcc_USB - USB analog power supply (3.3 V)
226 USB1_P I/O USB1 data input/output (+)
227 USB1_M I/O USB1 data input/output (-)
228 Avss_USB - USB analog power supply (0 V)
229 USB2_P I/O USB2 data input/output (+)
230 USB2_M I/O USB2 data input/output (-)
231 Avcc_USB - USB analog power supply (3.3 V)
232 Avss - A/D analog power supply (0 V)
233 AN[2]/PTL[2] I
234 AN[3]/PTL[3] I AD converter input
235 AN[4]/PTL[4] I
236 AN[5]/PTL[5] I
237 Avcc - A/D analog power supply (3.3 V)
238 AN[6]/PTL[6]/DA[1] I AD converter input
239 AN[7]/PTL[7]/DA[0] O DA converter output (LCD contrast)
240 Avss - A/D analog power supply (0 V)
CPUM: IC002
CPUP: IC002
FUNCTION