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UX-A7DVD
Pin No.
Symbol
79
CLKSEL
80
MADDR9
81
MADDR8
82
VDD_3.3
83
VSS
84
MADDR7
85
MADDR6
86
MADDR5
87
VDD_2.5
88
VSS
89
MADDR4
90
MWE
91
SD-CAS
92
VDD_3.3
93
VSS
94
SD-RAS
95
SD-CS0
96
SD-CS/MADDR11
97
SD-BS
98
MADDR10
99
MADDR0
100
VDD_3.3
101
VSS
102
MADDR1
103
MADDR2
104
MADDR3
105
RESERVED
106
NC
107
NC
108
RESERVED
109
NC
110
RESERVED
111
RESERVED
112
RESERVED
113
DAI-LRCK
114
DAI-BCK
115
VDD_3.3
116
VSS
117
DAI-DATA
118
DA-DATA3
119
DA-DATA2
120
DA-DATA1
121
DA-DATA0
122
DA-LRCK
123
VDD_3.3
124
VSS
1-62 (No.22013)
I/O
I
Selects SYSCLK or VCLK as clock source. Normal operation is to tie HIGH.
O
SDRAM address
O
SDRAM address
-
Power supply terminal 3.3V
-
Connect to ground
O
SDRAM address
O
SDRAM address
O
SDRAM address
-
Power supply terminal 2.5V
-
Connect to ground
O
SDRAM address
O
SDRAM write enable
O
Active LOW SDRAM column address
-
Power supply terminal 3.3V
-
Connect to ground
O
Active LOW SDRAM row address
O
Active LOW SDRAM chip select 0
O
Active LOW SDRAM chip select 1 or use as MADDR11 for larger SDRAM
O
SDRAM bank select
O
SDRAM address
O
SDRAM address
-
Power supply terminal 3.3V
-
Connect to ground
O
SDRAM address
O
SDRAM address
O
SDRAM address
I
Tie to VSS or VDD_3.3 as specified in table 1
-
Non connect
-
Non connect
I
Tie to VSS or VDD_3.3 as specified in table 1
-
Non connect
I
Tie to VSS or VDD_3.3 as specified in table 1
I
Tie to VSS or VDD_3.3 as specified in table 1
I
Tie to VSS or VDD_3.3 as specified in table 1
I
PCM left/right clock
I
PCM input bit clock
-
Power supply 3.3V
-
Connect to ground
I
PCM data input
O
PCM data output. Eight channels. Serial audio samples relative to DA_BCK and DA_LRCK
O
PCM data output. Eight channels. Serial audio samples relative to DA_BCK and DA_LRCK
O
PCM data output. Eight channels. Serial audio samples relative to DA_BCK and DA_LRCK
O
PCM data output. Eight channels. Serial audio samples relative to DA_BCK and DA_LRCK
O
PCM left clock. Identifies the channel for each sample
-
Power supply terminal 3.3V
-
Connect to ground
Description
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