65DRV
1-2 MAINBOARD LAYOUT --- 65DRV
AC'97
Codec
1
LPC I/O
Controller
WOL1
CNR 1
Using non-compliant memory with higher bus clock (over clocking)
may severely compromise the integrity of system.
RT1
VT8633
Clock
Generator
AGP PRO 4X
1
3
PCI 1
FAN2
PCI 2
JCD_IN1
4
PCI 3
PCI 4
PCI 5
PCI 6
USB2
12
1
3
FAN1
VIA
LED1
IDE1
IDE2
VIA
VT8233
16
16
USB3
1
1
JDIMM1
1
3
1
3
JDIMM2
Li
Battery
1
3
JBAT1
14
1
SCR1
ON
DIP
SW1
1 2 3 4
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