Lop Bus Interface; Miscellaneous Status And Control; Keyboard Block Diagram - HP 9020 Service Manual

lOP BUS
lOP BUS
C
INTERFACE
(50-PIN)
t
PC
(50-PIN)
POWER/MISCELLANEOUS
CONTROL
MISCELLANEOUS
STATUS AND CONTROL
~
DATA
R1,3,15
R11
BEEPER
Theory of Operation
2-31
OPTIONAL INPUT DEVICE
I
TB
(14-PIN)
t
KEYBOARD AND
KBDC
INPUT DEVICE
(20-PIN)
KEYSWITCH
SCANNING
BOARD
R10
R9,12
RTC/NVM
POWER-UP/
POWER-DOWN
LOGIC AND ENABLE
SENSE CIRCUITRY
KEYBOARD ELECTRONICS BOARD
Figure 2-19. Keyboard Block Diagram
lOP Bus Interface
The lOP bus data and control lines are buffered and interpreted at the interface circuitry. Sixteen
data lines and 14 control lines are present on the interface.
Four register select lines from the lOP indicate the assigned interface register on SC6 and therefore
determine the circuitry to be accessed.
Three peripheral address lines from the lOP must match the hard-wired SC6 decode circuitry to
access any keyboard circuitry.
Miscellaneous Status and Control
The following miscellaneous status and control circuits are discussed below: keyboard 10 register,
status buffer, service request latch, and bus test latches.
When the lOP requests a read of interface register 3 (R3) on SC6, the keyboard 10 register sets data
bus bit 1 to a 1. With O's on the other 7 lines of the lower 8 bits, the lOP recognizes that the
keyboard is present.
The status buffer presents three bits of status to the lOP upon reading of R1. The bits are as follows:
bit 0 - keyboard interrupt pending
bit 1 - power fail warning
bit 2 - (not used)
bit 3 - battery failure