Memory Healing - HP 9020 Service Manual

Theory of Operation
2-27
When using the 1 Megabyte RAM boards, a unique feature is employed. The Ram boards are
interleaved for better efficiency in memory access. This interleaving means that consecutive addres-
ses are found on different 1 Megabyte boards. Interleaving can be between 2, 4, or eight boards.
Whenever 1 Megabyte boards are used they will be used in pairs so this feature can be utilized to its
best advantage. The stack can support up to ten 1 Megabyte boards and the appropriate interleave
method for each configuration will be implemented automatically. If two boards are used, all the
odd numbered addresses are on one board and the even numbered addresses are on the other
board. Consecutive addresses will alternate between the boards. If four boards are used, consecu-
tive addresses move from one board to the next. For example: address 0 may be on board one;
address 1 on board two; address 2 on board three; address 3 on board four; and address 4 on
board one; etc. It is not necessary to change anything on the boards, as the operating system
automatically controls the set-up of interleaving for the best operation of the computer regardless of
the number of RAM boards or the mixture of 256K, 512K, or 1 Megabyte boards. Mapper CAM
data bits 9, 10, and. 11 are used to ensure that the mapper CAM responds to the correct interleave
method implemented by the operating system.
Even with the interleaving, the program speed of the 1 Megabyte RAM boards may be slightly
slower on some programs, when compared to the program speed using the 256K or 512K RAM
boards. This is due to the slower access time of the 1 Megabyte RAM boards.
Error Detection and Correction
As in the other memory boards, the Memory Controller detects and corrects single bit errors in data
read from RAM. It also detects double bit errors. Each 32 bit word written to memory has a 7 bit
Hamming code attached to it. When the data word is read, a single bit or double bit error is
detected.
Any single bit error that is detected is automatically corrected before the word is transferred to the
MPB. No additional time is required for the correction. At the same time that a single bit error is
detected and corrected, the correct data is written into a healer location.
A double bit error is detected but not corrected. A double bit error causes the system to halt,
preventing continuation of a program with bad data.
Memory Healing
Each Memory Controller contains 32 words each of CAM and RAM which are used to replace up to
32 failed memory words (Figure 2-18). The physical address of a failed word is put in the healer
CAM, and the corrected data is put in the corresponding healer RAM location. Bit 0 in the CAM is
set to enable the address to be matched. Subsequent accesses to this physical address are to the
healer RAM instead of the failed memory, causing the healer word to replace the failed word.
Healing does not affect the timing of the memory operation. Except for the healer, no record of
healing is stored in memory.
All mapped addresses are sent to the healer CAM, which compares each mapped address to all
addresses of failed locations.· Healer CAM addresses of failed locations have bit 0 set.