HP 124708-001 - ProLiant Cluster - 1850 Introduction Manual
The intel processor roadmap for industry-standard servers technology brief, 10 edition
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The Intel
processor roadmap for industry-
®
standard servers
technology brief, 10
Abstract ..............................................................................................................................................2
Introduction .........................................................................................................................................2
Intel processor architecture and microarchitectures ...................................................................................2
Hyper-pipeline and clock frequency ....................................................................................................5
Hyper-Threading Technology..............................................................................................................7
NetBurst microarchitecture on 90nm silicon process technology .............................................................9
Two-core technology .......................................................................................................................11
Intel Core™ microarchitecture ..............................................................................................................12
Processors......................................................................................................................................12
Xeon two-core processors ................................................................................................................12
Xeon four-core processors ................................................................................................................13
Integrated memory controller............................................................................................................15
Three-level cache hierarchy ..............................................................................................................17
Dynamic Power Management...........................................................................................................19
Performance comparisons....................................................................................................................20
TPC-C performance .........................................................................................................................20
SPEC performance ..........................................................................................................................20
Conclusion ........................................................................................................................................21
For more information ..........................................................................................................................22
Call to action .....................................................................................................................................22
th
Edition
®
microarchitecture ...................................................................................................................5
Extended hyper-pipeline...............................................................................................................10
SSE3 instructions.........................................................................................................................10
64-bit extensions -Intel 64 ..........................................................................................................10
Enhanced SpeedStep® Technology ...............................................................................................14
Intel Virtualization® Technology....................................................................................................15
®
Microarchitecture Nehalem .........................................................................................................15
QuickPath Technology ............................................................................................................16
®
Hyper-Threading Technology ...................................................................................................18
®
®
Turbo Boost Technology ..........................................................................................................18
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Summary of Contents for HP 124708-001 - ProLiant Cluster - 1850
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Page 1: Table Of Contents
The Intel processor roadmap for industry- ® standard servers technology brief, 10 Edition Abstract ..............................2 Introduction ............................2 Intel processor architecture and microarchitectures ...................2 NetBurst ® microarchitecture ........................5 Hyper-pipeline and clock frequency ....................5 Hyper-Threading Technology......................7 NetBurst microarchitecture on 90nm silicon process technology .............9 Extended hyper-pipeline.......................10 SSE3 instructions.........................10 64-bit extensions —Intel 64 ......................10... -
Page 2: Abstract
Abstract Intel ® continues to introduce processor technologies that boost the performance of x86 processors in multi-threaded environments. This technology brief describes these processors and some of the more important innovations as they affect HP industry-standard enterprise servers. Introduction As standards-based computing has pushed into the enterprise server market, the demand for increased performance and greater variety in processor solutions has grown. - Page 3 Intel processor sequences are intended to help developers select the best processor for a particular platform design. Intel offers three processor number sequences for server applications (see Table 1). Intel processor series numbers within a sequence (for example, 5100 series) help differentiate processor features such as number of cores, architecture, cache, power dissipation, and embedded Intel technologies.
- Page 4 Table 2 includes more details about the release dates and features of previously released Intel x86 processors, as well as processors projected to be available through 2009. Release dates and features of Intel x86 processors Table 2. Code Market Feature Description Available/ Cache...
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Page 5: Netburst ® Microarchitecture
NetBurst ® microarchitecture The NetBurst-based processor for low-cost, single-processor servers is the Pentium® 4 processor. The original 180nm version of the Pentium 4 was known as Willamette, and the subsequent 130nm version was known as Northwood. NetBurst-based processors intended for multi-processor environments are referred to as Intel®... - Page 6 Figure 3. By decreasing the amount of work done in each stage, the clock frequency can be increased. A basic structure for a computer pipeline consists of the following four steps, which are performed repeatedly to execute a program. Fetch the next instruction from the address stored in the program counter. Store that instruction in the instruction register, decode it, and increment the address in the program counter.
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Page 7: Hyper-Threading Technology
Keeping the pipeline busy requires that the processor begin executing a second instruction before the first has traveled completely through the pipeline. However, suppose a program has an instruction that requires summing three numbers: X = A + B + C If the processor already has A and B stored in registers but needs to get C from memory, this causes a “bubble,”... - Page 8 Since multi-processing operating systems such as Microsoft Windows and Linux are designed to divide their workload into threads that can be independently scheduled, these operating systems can send two distinct threads to work their way through execution in the same device. This provides the opportunity for a higher abstraction level of parallelism at the thread level rather than simply at the instruction level, as in the Pentium 4 design.
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Page 9: Netburst Microarchitecture On 90Nm Silicon Process Technology
HT Technology also puts a heavier load on the OS to allocate threads and switch contexts on the device. Evaluating the threads for parallelism and context switching are OS tasks and increase the operating overhead. HT Technology presents little in the way of software licensing issues. Intel asserts that the HT design is still only a single-processor unit, so customers should not have to purchase two software licenses for each processor. -
Page 10: Extended Hyper-Pipeline
Extended hyper-pipeline In keeping with its history of regularly increasing processor frequencies, Intel extended the hyper- pipeline queue from 20 (in the earlier Pentium 4 design) to 31 stages. The biggest drawback to this approach is that, as the pipe gets longer, interruptions (stalls) to the regular flow of instructions in the pipe become progressively more costly in terms of performance. -
Page 11: Two-Core Technology
Two-core technology Single-core processors that run multi-threaded applications become less cost effective with each increase in frequency. This is because the multiple threads compete for available compute resources, which limits the increase in performance at higher frequencies. Increasing the CPU core frequency not only delivers lower incremental performance gains, but also increases power requirements and heat generation. -
Page 12: Intel Core™ Microarchitecture
Intel Core™ microarchitecture In 2006, Intel introduced the Core microarchitecture to extend the NetBurst microarchitecture features and to add the energy efficient features of Intel’s mobile microarchitecture. The Core microarchitecture uses less power and produces less heat than previous generation Intel processors. The Core microarchitecture features the following technologies that improve per-watt performance and energy efficiency: •... -
Page 13: Xeon Four-Core Processors
The 64-bit Xeon 5100 series two-core processor runs at a maximum frequency of 3.0 GHz with 4 MB of shared L2 cache and a maximum front-side bus speed of 1333 megahertz (Figure 7 right). The Xeon 5000 Sequence as well as the 5100 and 5200 series processors use the Intel 5000 series chipsets. -
Page 14: Enhanced Speedstep® Technology
The four-core Intel Xeon 7300 series processor (Tigerton) consists of two dual-core silicon chips on a single ceramic module, similar to the Xeon 5300 series processors. Each pair of cores shares a L2 cache; up to 4 MB of L2 cache can be allocated to one core. Intel states the Xeon 7300 series processors offer more than twice the performance and more than three times the performance-per-watt of the previous generation 7100 series, which is based on the NetBurst microarchitecture. -
Page 15: Intel Virtualization® Technology
Intel Virtualization® Technology Virtualization techniques that are completely enabled in software perform many complex translations between the guest operating systems and the hardware. With software virtualization, the processor overhead increases (performance decreases) as each guest OS and application vies for the host machine’s physical resources such as memory space and I/O devices. -
Page 16: Intel ® Quickpath Technology
Intel Microarchitecture Nehalem Figure 10. Intel QuickPath Technology ® Intel QuickPath Technology maximizes data transfer between the processors and other system components. It replaces the multi-drop front-side bus and memory controller hub found in previous generation architectures with high-speed, point-to-point interconnects that directly link the processors and I/O chipset (Figure 11). -
Page 17: Three-Level Cache Hierarchy
Three-level cache hierarchy Each Intel Xeon 5500 series processor has a three-level cache hierarchy (Figure 11): • An on-die, 64-kilobyte, L1 cache that is split into two 32-kilobyte caches storing data and instructions • An individual, 256-kilobyte, L2 cache for each core for lower latency •... -
Page 18: Intel ® Hyper-Threading Technology
Intel Hyper-Threading Technology ® Intel Nehalem-based processors re-introduce the support for HT Technology (simultaneous multi- threading). HT Technology lets each core execute two computational threads at the same time, which allows each four-core processor to simultaneously execute up to eight threads. In addition, the high- bandwidth memory subsystem supplies data faster to the two computational processes, and the low- latency cache hierarchy allows simultaneous processing of more instructions. -
Page 19: Dynamic Power Management
heat savings realized by disabling processor cores allows the remaining cores to run at a higher frequency than their rated speed. In specific application environments, this may actually increase overall system performance. • Addressing licensing issues. Some software is licensed on a per-core basis. Disabling cores allows an administrator to match the number of active cores on a server with licensing requirements. -
Page 20: Performance Comparisons
Performance comparisons TPC-C performance The Transaction Processing Performance Council benchmark TPC-C results for Woodcrest, Clovertown, Tulsa, Nehalem, and Dunnington processors are compared in Figure 14. TPC-C is measured in transactions per minute (tpmC). Figure 14. TPC-C performance for Intel processors showing percentage improvements compared to Woodcrest SPEC performance The Standard Performance Evaluation Corporation (SPEC) CPU2006 benchmark provides performance measurements that can be used to compare compute-intensive workloads on different... -
Page 21: Conclusion
Figure 15. SPEC CPU2006 performance for Intel processors showing percentage improvements compared to Woodcrest Conclusion Intel processors continue to provide dramatic increases in the processing capability of HP industry- standard servers. In addition to improved system performance, multi-core Intel processors offer greater energy efficiency to help HP customers manage power costs. -
Page 22: For More Information
For more information For additional information, refer to the resources listed below. Resource description Web address ProLiant servers home page www.hp.com/servers/proliant Power Regulator for ProLiant http://h20000.www2.hp.com/bc/docs/support/Su Servers pportManual/c00300430/c00300430.pdf ISS Technology Papers www.hp.com/servers/technology Call to action Send comments about this paper to TechCom@HP.com ©...