HP 9020 Service Manual page 88

3-6
Testing and Troubleshooting
The CPU chip contains a revision identifier accessible by the operating system. The revision
identifier is the microcode release date. The format is VYYYMMDD where YYVY is the year, MM is
the month, and DO is the day.
lOP Finstrate
Each lOP in the stack initiates its self-test. Internal hardware registers are tested for read/write
ability, and the MPB interface is tested for the ability to communicate on the MPB. Successful
c<?91pletion of the self-test indicates a greater than 95% confidence in the lOP chip, board integrity,
and MPB/IOP connection. The self-test does not test the printed circuit lOP buffer card which plugs
into the lOP finstrate. This card is tested on powerup by the self-test supervisory code resident in
the operating system.
The lOP chip contains a revision identifier accessible by the operating system. The revision identi-
fier is the microcode release date. The format is YYVYMMDD where YYVY is the year, MM is the
month, and DO is the day.
RAM Boards
Each memory controller first performs a self-test and then a memory test in parallel with other
memory controllers. The self-test checks all of the memory controller circuits, data paths, and
operations except the sending of messages on the MPB which is deferred until after the memory
test. The memory controller purposely introduces a double-bit failure so the CPU can test the error
detection and notification process.
The memory test consists of pattern-testing the memory to distinguish between non-existent mem-
ory, good RAM, and RAM with hard failures. If a faulty location is detected, a flag is set to indicate
that the 16K-byte memory block in which the failure was detected is suspect. The self-test supervis-
ory code tests these blocks later to determine if the failure is correctable or if the block should
remain "mapped out".
The RAM boards provide 256K, 512K, or 1 Megabyte of RAM per board. The boards contain
memory chips and a memory controller chip (MC). Double bit error detection and single bit
correction require part of the memory chip capacity. There are enough memory chips on the board,
so that 256K, 512K, or 1 Megabyte of memory is still available after the double bit and single bit
requirements are met.
The MC interfaces the memory processor bus and memory. It also does error detection and
correction, memory mapping, and memory healing. At powerup the MC does a self-test. The
self-test supervisory code then tests RAM memory by executing writes and reads to each location.
The MC does a Hamming code check. If an error occurs, the associated 16K-byte block of memory
is mapped out.
If a single-bit error is detected during run time, the MC corrects the bit and sends the corrected
word. The MC then performs the memory healing process by copying the corrected word into one
of 32 healing locations within the MC. The corrected word is copied into a healing location. On
subsequent accesses to the location which had produced the error, the MC reads the healer
location instead. There is no degradation in memory access time.