Panasonic SA-BT100P Service Manual page 101

1 2 3
SCHEMATIC DIAGRAM - 5
A
A
DIGITAL (PEAKS PRO2) CIRCUIT
DN PK_D1R2V_C
ST_D3R3V
DN
QR51001
DN XPKRST
B1GDCFGG0028
SWITCH
B
EX XTRST0
EX XRST
1 5
QR51002
2
B1GDCFGG0028
SWITCH
3 4
IC51002
C0EBE0000368
RESET
C
DN DGND
DN PKS_STATE
PEAKS-Pro RESET
XRST A16
D
XSRST F17
E
LB51004
J0JYC0000070
LB51005
J0JYC0000070
VCXO #1
F
FL51012
F1H0J4740004
G_CK74_B
R51018 47
CK74A F28
R51006
0
VSELA C28
FL51011
F1H0J4740004
G
C51013
7P
C51014
7P
FL51007
F1H0J4740004
R51008
R51013
1.5K
G_VC27A_A G_VC27A_B
VC27A B29
R51014
H
1 2 3
4 5 6
: +B SIGNAL LINE
LB51001 FL51001
J0JYC0000070 F1H0J4740004
7 5 3 1
RX51001
D1H84724A024
8 6 4 2
FL51002
F1H0J4740004
QR51003
B1GBCFGG0024
SWITCH
QR51004
B1GBCFGG0024 LB51002
FL51003
J0JYC0000070
F1H0J4740004
SWITCH
LB51003
FL51004
J0JYC0000070
F1H0J4740004
FL51005
F1H0J4740004
FL51006
F1H0J4740004
R51054
47
G_CK27A0_A
IC51003
1 TEST_I CLK27M1 28
C1CB00002777
CLOCK GENERATOR G_CK27A_A G_CK27A_B
2
CLK54M CLK27M2 27
FL51018
R51031
F1H0J4740004
47
3 VDD_HD VDD_SD 26
4 VSS_HD VSS_SD 25
R51033
47
G_A1EXCK_A
G_CK74_A G_A1EXCK_B
5 HDCLK MCLK 24
FL51021
R51053
F1H0J4740004
47
6 SEL_HD VDD 23
7 VDDA VSS 22
C51039
0.1
CLK36M
8 VSSA 21
R51038
X51001
47
H0J270500112
9
XTAL_IN SEL_MC1 20
R51023
390
10 XTAL_OUT CLK384FS 19
C51017
1
11 VDD_V OE 18
R51019
51K
6.8K
12 VCTRL 17
CLK_MODEM
C51018
6.8K 1
13 VSS_V TEST_A 16
C51036 R51039
0.1 47
14 TEST_H 15
SEL_MC0
4 5 6
7 8 9
VDDIO(3.3V)
FL51009
D8 VDD33
LB51007
F1H0J4740004
D12 VDD33
J0JGC0000020
C51022 0.1
D16 VDD33
C51023 0.1
P33 AVDD_APLL2
D20 VDD33
C51024 0.1
D24 VDD33
C51026 0.1
R29 AVSS_APLL2
N21 VDD33
LB51008 P22 VDD33
FL51014
J0JGC0000020
F1H0J4740004
R22 VDD33
T28
AVDD_APLL1
A32 VDD33
R30 AVSS_APLL1
A33 VDD33
C51027 0.1
A34 VDD33
C51028 0.1
R34 AVDD_MPLL_2
B32 VDD33
C51030 0.1
C32 VDD33
D31 VDD33
E30 VDD33
T29 AVDD_MPLL_1
F29 VDD33
G28 VDD33
L31 VDD33
AA31 VDD33
AE31 VDD33
AG7 AVDD_DPL
AH8 AVSS_DPLL
T33 AVDD_RX1_SATA
T34
AVSS_RX1_SATA
W33 AVDD_TX1_SATA
W34 AVSS_TX1_SATA
IC51001
MN2WS0043AP
Y34 AVDDBGR_SATA
PEAKS-PRO2
R31 AVSS_TRM_SATA
U28 AVSS_TRM_SATA
U29 AVSS_TRM_SATA
U30 AVSS_TRM_SATA
U31 AVSS_TRM_SATA
U32 AVSS_TRM_SATA
X51003
C51095
V32 AVSS_TRM_SATA C51097
H0J250500069
12P 15P
T30
AVSS_TRM_SATA
IC51005
C1CB00002408
CLOCK GENERATOR
1 X1/CLK X2 8
FL51028
F1H0J4740004
G_CK27A0_B
DH 2 VDD VDD 7
C51096
0.1
A31 CK27A
3 GND 33.3M 6
G_CK33IN_B
4 CLK 33.3M 5
B30 AEXCKA
DH : DIGITAL (DAC HDMI) : SCHEMATIC DIAGRAM -1 ~ 2
G_768FSA_B AI
DN : DIGITAL (DIGITAL NET) : SCHEMATIC DIAGRAM - 3 ~ 4
PK : DIGITAL (PEAKS PRO2) : SCHEMATIC DIAGRAM - 5 ~ 6
AI : DIGITAL (AUDIO I/O) : SCHEMATIC DIAGRAM - 7
PE : DIGITAL (PRO2 PERI) : SCHEMATIC DIAGRAM - 8 ~ 9
EX : DIGITAL (PRO2 EXBUS) : SCHEMATIC DIAGRAM - 10 ~ 11
B28 ASEL1A
D0 : DIGITAL (PRO2 DDR2 CH0) : SCHEMATIC DIAGRAM - 12 ~ 13
D1 : DIGITAL (PRO2 DDR2 CH1) : SCHEMATIC DIAGRAM - 13 ~ 14
ET : DIGITAL (PRO2 ETHER) : SCHEMATIC DIAGRAM - 16
F27 ASEL0A
7 8 9
101
10 11 12
FL51022 VDDIO(1.2V)
F1H0J4740004
C1 VDD
C51040 10
LB51012 C2 VDD
J0JGC0000020 C51041 0.01
D2 VDD
C51042 0.01
D3 VDD
C51043 0.01
E4
VDD
F5 VDD
G6
VDD
H7 VDD
LB51013 FL51023 FL51023 K4
VDD
J0JGC0000020
F1H0J4740004 F1H0J4740004
L4 VDD
N14 VDD
C51047 10
N15 VDD
C51048 0.01
N16 VDD
C51049 0.01
N17 VDD
C51050 0.01
P15 VDD
P16 VDD
P17 VDD
R13 VDD
R16 VDD
R17 VDD
FL51024 T13 VDD
LB51014
F1H0J4740004
J0JGC0000020
T14
VDD
N19 VDD
C51057 10
N20 VDD
C51058 0.01
P19 VDD
C51059 0.01
T21
VDD
LB51015
FL51025
T22 VDD
J0JGC0000020
F1H0J4740004
V20 VDD
C51062 10
V21 VDD
C51063 0.01
V22 VDD
C51064 0.01
W20 VDD
0.01
C51065
W21 VDD
W22 VDD
Y21 VDD
Y22 VDD
AA22 VDD
LB51016 FL51026 AB19 VDD
J0JGC0000020
F1H0J4740004
AB20 VDD
AH28 VDD
C51069 10
AJ29 VDD
C51070 0.01
AK30 VDD
0.01
C51071
AL31 VDD
C51072 0.01
AM32 VDD
AN33 VDD
AN34 VDD
AL24 VDD
AL25 VDD
PEAKS-Pro CLOCK
SYSTEM CLOCK
A29 CK33XO
R51045
100
G_CK33XI_B
A28 CK33XI
AP2 CK33IN
R51046
100 DDR2 PLL CLOCK
1/2 2/2
SA-BT100P/PC DIGITAL (PEAKS PRO2) CIRCUIT
10 11 12
SA-BT100P / SA-BT100PC
13 14
TO DIGITAL
(PEAKS PRO2)
SECTION (2/2)
13 14