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LG 50PQ30 Training Manual

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Training Manual
50PQ30 Plasma Display
50PQ30 Plasma Display
Advanced Single
Scan Troubleshooting
720p
720p
Published November 05
, 2009
th

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Table of Contents
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  Summary of Contents for LG 50PQ30

  • Page 1 Training Manual 50PQ30 Plasma Display 50PQ30 Plasma Display Advanced Single Scan Troubleshooting 720p 720p Published November 05 , 2009...
  • Page 2 Lower board delivers Scan to Upper • Z-SUS Output Board (Also uses one Z-SUB board for bottom panel connector) • Control Board • X Drive Boards (3) • Main Board • Main Power Switch (Version 3). Shuts off stand by 5V. November 2009 50PQ30 Plasma...
  • Page 3 Layout of the Plasma Display Panel. At the end of this Section the Technician should be able to Identify the Circuit Boards and have the ability and knowledge necessary to safely remove and replace any Circuit Board or Assembly. November 2009 50PQ30 Plasma...
  • Page 4: Important Safety Notice

    When servicing this product, under no circumstances should the original design be modified or altered without permission from LG Electronics. Unauthorized modifications will not only void the warranty, but may lead to property damage or user injury.
  • Page 5 Alignment Handbook the Learning Academy site the Learning Academy site the Plasma page the Plasma page Published November 2009 by LG Technical Support and Training LG Electronics Alabama, Inc. 201 James Record Road, Huntsville, AL, 35813. Page 5 Page 5...
  • Page 6: Regulatory Information

    Increase the separation between the equipment and the receiver; Connect the equipment to an outlet on a different circuit than that to which the receiver is connected; or consult the dealer or an experienced radio/TV technician for help. November 2009 50PQ30 Plasma...
  • Page 7 1. Check the appearance of the Replacement Panel and Circuit Boards for both physical damage and part number accuracy. 2. Check the model label. Verify model names and board model matches. 3. Check details of defective condition and history. Example: Y Board Failure, Mal-discharge on screen, etc. November 2009 50PQ30 Plasma...
  • Page 8 • Correct The final step is to correct the problem. Be careful of ESD and make sure to check the DC Supplies for proper levels. Make all necessary adjustments and lastly always perform a Safety AC Leakage Test before returning the product back to the Customer. November 2009 50PQ30 Plasma...
  • Page 9 50PQ30 PRODUCT INFORMATION SECTION 50PQ30 PRODUCT INFORMATION SECTION This section of the manual will discuss the specifications of the 50PQ30 Advanced Single Scan Plasma Display Television. November 2009 50PQ30 Plasma...
  • Page 10 • 3x HDMI™ V.1.3 with Deep Color (2 Rear, 1 side). • AV Mode (Cinema, Sports, Game) • Clear Voice • LG SimpLink™ Connectivity • Invisible Speaker System • 100,000 Hours to Half Brightness (Typical) • PC Input November 2009 50PQ30 Plasma...
  • Page 11 600 Hz Sub Field Driving is achieved by using 10 sub-fields per frame process (vs. Comp. 8 sub-field/frame) • No smeared images during fast motion scenes Original Image 10 Sub Fields Per Frame Sub Field firing occurs using wall charge and polarity differences between Y-SUS and Z-SUS signals. November 2009 50PQ30 Plasma...
  • Page 12 Specifications Logo Familiarization (Picture Wizard) Specifications Logo Familiarization (Picture Wizard) Picture Wizard easily guides consumers through the calibration process using on-screen reference points. Customers can customize picture performance without the need for additional expense. November 2009 50PQ30 Plasma...
  • Page 13 50PQ30 Logo Familiarization Page 1 of 2 50PQ30 Logo Familiarization Page 1 of 2 HD RESOLUTION 720p HD Resolution Pixels: 1365 (H) × 768 (V) High definition television is the highest performance segment of the DTV system used in the US. It’s a wide screen, high-resolution video image, coupled with multi-channel, compact-disc quality sound.
  • Page 14 50PQ30 Logo Familiarization Page 2 of 2 50PQ30 Logo Familiarization Page 2 of 2 AV Mode "One click" Cinema, Cinema, Sport, Game mode. TAKE IT TO THE EDGE is a true multimedia TV with an AV Mode which allows you to choose from 4 different modes of Cinema, Sports and Game by a single click of a remote control.
  • Page 15 50PQ30 Remote Control 50PQ30 Remote Control TOP PORTION BOTTOM PORTION November 2009 50PQ30 Plasma...
  • Page 16 50PQ30 Rear and Side Input Jacks 50PQ30 Rear and Side Input Jacks Music and Software Photos Upgrades SIDE INPUTS HDMI 3 AC In REAR INPUTS November 2009 50PQ30 Plasma...
  • Page 17 50PQ30 Dimensions Power: There must be at least 4 inches of Clearance on all sides 279W (Typical) 3-5/16" 47-7/8" 0.13W (Stand-By) 83.82mm 1216.66mm 6-3/16" 157mm 15-3/4" 400mm 15-5/16" 405mm 32-3/16" 15-3/4" 15-3/4" 817.9mm 400mm 400mm Model No. Serial No. 29-7/8"...
  • Page 18 DISASSEMBLY SECTION This section of the manual will discuss Disassembly, Layout and Circuit Board Identification, of the 50PQ30 Advanced Single Scan Plasma Display Panel. Upon completion of this section the Technician will have a better understanding of the disassembly procedures, the layout of the printed circuit boards and be able to identify each board.
  • Page 19 To remove the back cover, remove the 26 screws (The Stand does not need to be removed). Indicated by the arrows. PAY CLOSE ATTENTION TO THE TYPE, SIZE AND LENGTH Of the screws when replacing the back cover. Improper type can damage the front. November 2009 50PQ30 Plasma...
  • Page 20 Power Supply (SMPS) Z-SUS Y-SUS Z-SUB Side Input Control (part of main) Heat Sink Main Board Y-Drive AC In Lower Left “X” Center “X” Right “X” Main Conductive Tape Under Main Board Invisible Speakers Keyboard Power November 2009 50PQ30 Plasma...
  • Page 21 P107, P109 and/or P205, P206 and P208 from the Y-SUS Board. Collar Note: Y, Z-SUS and Y-Drive boards are mounted on board stand-offs that have a small collar. The board must be lifted slightly to clear these collars. November 2009 50PQ30 Plasma...
  • Page 22 Remove the 2 screws holding the Key board in place. Remove the board by releasing the two black tabs and lifting the board upward. Disconnect P101. (Note: LED board is behind the Key board. Remove it’s 2 screws and remove. Disconnect J1 and J2. November 2009 50PQ30 Plasma...
  • Page 23 Disconnect all TCP ribbon cables from the defective X-Drive board. Remove the 3 screws in either the Left or Right X-Drive board or the 4 screws holding the Center X-Drive in place. Remove the board. Reassemble in reverse order. Recheck Va / Vs / VScan / -VY / Z-Drive. November 2009 50PQ30 Plasma...
  • Page 24 Getting to the X Circuit Boards Warning: Never run the TV with the TCP Heat Sink removed LVDS Cable Stand should have already be removed Right Left Heat Sink Warning Shorting Hazard: Conductive Tape. Do not allow to touch energized circuits. November 2009 50PQ30 Plasma...
  • Page 25 It may stick, be careful not to crack TCP. (See next page for precautions) Removing Connectors to the TCPs. Gently lift the locking mechanism upward on all TCP connectors Left X: P101~105 Center X: P201~206 Cushion (Chocolate) Right X: P301~305 Flexible ribbon cable connector November 2009 50PQ30 Plasma...
  • Page 26 Pull TCP apart as shown by arrow. Note: TCP is usually stuck down (TCP Film can be easily damaged. to the heat transfer material, be Handle with care.) Very careful when lifting up on the TCP ribbon cable. November 2009 50PQ30 Plasma...
  • Page 27 The Left X Board drives the right side of the screen vertical electrodes The Center X Board drives the Center of the screen vertical electrodes The Right X Board drives the left side of the screen vertical electrodes November 2009 50PQ30 Plasma...
  • Page 28 At the end of this Section the technician should understand the operation of each circuit board and how to adjust the controls. The technician should be able with confidence to troubleshoot a circuit board failure, replace the defective circuit and perform all necessary adjustments. November 2009 50PQ30 Plasma...
  • Page 29: Main Board

    50PQ30 SIGNAL and VOLTAGE DISTRIBUTION DIAGRAM Y Drive 5VFG indicates SMPS OUTPUT VOLTAGES IN RUN Horizontal Upper measured from SMPS OUTPUT VOLTAGES IN STBY Display Panel Floating Ground STB5V, +5V, 17V, 12V to Main PWB FPCs STB +5V (also AC Voltage Det)
  • Page 30 (12) Panel Model Name (5) Adjusting Voltage (Set Up / -Vy / Vsc / Ve / Vzb) (13) Max. Watt (Full White) (6) Trade name of LG Electronics (14) Max. Volts (7) Manufactured date (Year & Month) (15) Max. Amps...
  • Page 31 1) When the Y-SUS board is replaced 2) When a “Mal-Discharge” problem is encountered All label references are from a specific panel. 3) When an abnormal picture issues is encountered They are not the same for every panel encountered. November 2009 50PQ30 Plasma...
  • Page 32 Check the silk screen label on the top center of the Power Supply board to identify the correct part number. (It may vary in your specific model number). On the following pages, we will examine the Operation of this Power Supply. November 2009 50PQ30 Plasma...
  • Page 33 50PQ30 50G2 (SMPS) POWER SUPPLY BOARD 50PQ30 50G2 (SMPS) POWER SUPPLY BOARD Model : PDP 50G2#### EXAMPLE: Voltage Label. Use the voltage Voltage Setting:5V / Va:60V / Vs:193V label off your specific panel for adjustments. N.A. / -185 / 133 / N.A. / 80...
  • Page 34 There are 2 adjustments located on the Power Supply Board VA and VS. The Adjustments 5V VCC is pre-adjusted and fixed. All adjustments are made with relation to Chassis Ground. Use “Full White Raster” 100 IRE RV502 RV901 November 2009 50PQ30 Plasma...
  • Page 35 VA VR502 382V Run Fuse F801 VS VR901 4Amp/250V 160V Stby 382V Run Fuse F302 IC701 1Amp/250V STBY 5V Sub Micon Bridge 5V, 12V Rectifier Source Main Fuse F101 P813 10Amp/250V AC Input To MAIN SC 101 November 2009 50PQ30 Plasma...
  • Page 36 (opened), it pulls up and turns the Controller IC701 on in the Auto mode. In this state, the Controller turns on the power supply in stages automatically. A load is necessary to perform a good test of the SMPS if the Main board is suspect. November 2009 50PQ30 Plasma...
  • Page 37 50PQ30 POWER SUPPLY START UP SEQUENCE 50PQ30 POWER SUPPLY START UP SEQUENCE In Stand-By Primary side is 160V/123V Y DRIVE FG5V Standby 5V will not In Run (Relay On) Primary side is 386V Floating Gnd 5V Upper be output if the Main POWER SUPPLY Power Switch is off.
  • Page 38 Place voltmeter on pin 1 or 2 of P811. Adjust VR901 until the reading matches your label. Va Adjust: Place voltmeter on pin 6 or 7 of P811. Adjust VR502 until the reading matches your label. November 2009 50PQ30 Plasma...
  • Page 39 50PQ30 SMPS STATIC TEST UNDER LOAD Using two 100 Watt light bulbs, attach one end to Vs and the other end to ground. Apply AC to SC101. If the light bulbs turn on and VS is the correct voltage, allow the SMPS to run for several minutes to be sure it will operate under load. If this test is successful and all other voltages are generated, you can be fairly assured the power supply is OK.
  • Page 40 (E) 100Ω ¼ watt resistor added from STBY 5V (Pins 9 ~ 11) to VS ON (Pin 20) brings the • 17V (P813 pins 1 and 2) lines high. • VA and VS (P811 pins 1 and 2 Vs and Pins 6 and 7 Va) lines high. November 2009 50PQ30 Plasma...
  • Page 41 Main Power Switch is open. VS On command arrives. Stand-By 5V will shut off. Note: The 5V/12V turns on when the RL On command arrives. Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. November 2009 50PQ30 Plasma...
  • Page 42 1, 2 *194V Open 4, 5 6, 7 *60V Open 9, 10 0.86V * Note: This voltage will vary in accordance with Panel Label Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. November 2009 50PQ30 Plasma...
  • Page 43 To the Control Board then routed to the Z-SUS board Floating Ground FG 5V Used on the Y-Drive boards (Measured from Floating Gnd) FG 15V Used in the Development of the V-Scan signal (Measured from Floating Gnd) November 2009 50PQ30 Plasma...
  • Page 44 Also controls Set Up/Down Generates Floating Ground Left X Board 5V by DC/DC Converters FETs amplify Y-Sustain Waveform Logic signals needed to scan the panel Y-Drive Boards Receive Scan Waveform Display Panel Logic signals needed to generate drive waveform November 2009 50PQ30 Plasma...
  • Page 45 Control Board Pins 8 and 9 FS201 (Va) VSC TP 10A/125V FS501 (17V) R202 Pins 2 ~5 Logic (Drive) P207 4A/125V P202 Signals to the Y-Drive Va to Left X Board P202 Lower board Pins 5~7 November 2009 50PQ30 Plasma...
  • Page 46 Set should run for 15 minutes, this is the “Heat Run” mode. Set screen to “White Wash”. Adjust –Vy to Panel Label voltage (+/- 1V) Lower Center of board Adjust VSC to Panel Label voltage (+/- 1V) Just below Heat Sinks November 2009 50PQ30 Plasma...
  • Page 47 100uS/div (Top of Board) NOTE: The Waveform Test Points are fragile. If by accident the land is torn and the run lifted, make sure there are no lines left to right in the screen picture. 100uS November 2009 50PQ30 Plasma...
  • Page 48 Remember, this is the first large signal to the right of blanking. Fig 4: FIG4 At 40uSec per/division, the adjustment for SET-UP Area to 40uS be adjusted can be made. It will make this adjustment easier if you use the “Expanded” mode of your scope. November 2009 50PQ30 Plasma...
  • Page 49 Remember, this is the first large signal to the right of blanking. Area to be adjusted Fig 4: FIG4 At 20uSec per/division, the adjustment for 20uS SET-DN can be made. It will make this adjustment easier if you use the “Expanded” mode of your scope. November 2009 50PQ30 Plasma...
  • Page 50 (150V ± 5V) SET-DN ADJUST: 2) Adjust VR401 and set the (B) time of the signal to match the waveform above. (100uSec 5uSec) ADJUSTMENT LOCATIONS: Top Left and Center Right November 2009 50PQ30 Plasma...
  • Page 51 Full Counter Clock Wise Very little alteration to the picture, the wave form indicates a distorted SET UP. The peek widens due to the SET UP Ramp (SET UP) Too Low (80V) peeking too quickly. Full Clock Wise November 2009 50PQ30 Plasma...
  • Page 52 (SET DN) Too High 166uSec All of the center washes out due to increased SET_DN time. Full Clock Wise The center begins to wash out and arc due to decreased (SET DN) Too Low SET DN time. Counter Clock Wise November 2009 50PQ30 Plasma...
  • Page 53 Shown: 0.5V Shown: Open K3667 *Shown: 2.2V *Q18 Reverse: Open Reverse: Open *Reversed: 2.18V Reverse: Open Blk Red RF2001 Shown: Shorted Shown: 0.37V~0.38V Shown: 0.37~0.38V Reverse: Shorted Reverse: Open Reverse: Open 0.3 Ohms Blk Red D717 November 2009 50PQ30 Plasma...
  • Page 54 Reverse: Open Blk Red Shown: 0.668V Shown: 0.392V Shown: 0.998V 30J124 Reverse: 0.6V Reverse: Open Reverse: Open Blk Red Shown: Shorted Shown: 0.392V Shown: 0.392V RF020 Reverse: Shorted Reverse: Open Reverse: Open (0.3 Ohm) Blk Red November 2009 50PQ30 Plasma...
  • Page 55 P207 Pins 2, 3, 4, and 5 are 4) OC1 Logic (Drive) Signals to the 3) DATA Y-SUS Board Y-Drive Lower Y-Drive lower. 2) OC2 Board P209 carries the Y-Drive signals 1) Ground (F) to the upper via P108. Bottom Connector P207 November 2009 50PQ30 Plasma...
  • Page 56 0.66V 5) STB 1.43V 0.66V 4) OC1 1.43V 0.68V 3) DATA 1.53V 0.66V 2) OC2 1.53V 0.68V Floating Gnd 1) Ground (F) P207 Y-Drive Board should be disconnected for this test. Meter in the Diode Mode November 2009 50PQ30 Plasma...
  • Page 57 FG5V (+5V F) measured 5) 5V VF from Pins 4 or 5 to 4) 5V Vf Floating Gnd 3) Ground (F) Pins 1~3, 6 or 11 2) Ground (F) FL101 1) Ground (F) Top Connector P209 November 2009 50PQ30 Plasma...
  • Page 58 1.94V 0.68V 4) 5V VF 1.94V 0.68V Floating Gnd 3) Ground (F) Floating Gnd 2) Ground (F) Floating Gnd 1) Ground (F) P209 Y-Drive Board should be Meter in the Diode Mode disconnected for this test. November 2009 50PQ30 Plasma...
  • Page 59 STBY Diode Mode *193V Open *193V Open *60V Open *60V Open 0.86V 0.86V * Note: This voltage will vary in accordance with Panel Label Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. November 2009 50PQ30 Plasma...
  • Page 60 P202 CONNECTOR "Y-SUS" to "X-Drive” Left P122 Label STBY Diode Mode *60V Open *60V Open *60V Open * Note: This voltage will vary in accordance with Panel Label Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. November 2009 50PQ30 Plasma...
  • Page 61 Diode Mode 1, 2 0.86V 8, 9 Er Com *89V 11, 12 *193V Open * Note: This voltage will vary in accordance with Panel Label Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. November 2009 50PQ30 Plasma...
  • Page 62 Routed out P101 to the Control Board. Leaves the Control Board on P101 pins 11 and 12. Can also be checked at J642 15V TP. Standby: 0V Run: 15V Diode Check: Open Location: Bottom Center Right November 2009 50PQ30 Plasma...
  • Page 63 FG15V Test Point FG15V to develop the Y-Drive signal. Checked at J644 (+15V (F) Test Point. Standby: 0V Run: 15.2V Diode Check: 1.5V Location: Bottom Center of the Floating Ground J643 two large black heat sinks. November 2009 50PQ30 Plasma...
  • Page 64 Check Odd pins on Y-SUS board Check Even pins on Control board Only Odd pins are easily accessible with P101 Ribbon Cable Connector Label inserted Pin 29 Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. November 2009 50PQ30 Plasma...
  • Page 65 Ramp Slope OPT 1 3.12V 0.9V ER UP 0.14V 0.9V Blocking 1.1V 0.9V YSUS UP 0.11V 0.9V There are No Stand By Voltages on this Connector Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. November 2009 50PQ30 Plasma...
  • Page 66 Y-Sustain board and sent to the Panel through Scan Driver IC’s. The Y-Drive Boards supply a waveform which selects the horizontal electrodes sequentially starting at the top and scanning down the panel. * 50PQ30 uses 8 Driver ICs on 2 Y-Drive Boards TIP: See additional Service Tips beginning on page 131.
  • Page 67 Y-SUS. Y-Drive signal (VSC) Look carefully. from the Y-SUS board See Tip section through the Y-Drive page 133-134. lower is supplied to the Upper Y-Drive Board on Connector P108. PANEL Y-SUS SIDE SIDE November 2009 50PQ30 Plasma...
  • Page 68 FG5V (+5V F) measured 5) 5V VF from Pins 4 or 5 to 4) 5V VF Floating Gnd 3) Ground (F) Pins 1~3, 6 or 11 2) Ground (F) 1) Ground (F) FL101 P209 P109 Top Connector P109 November 2009 50PQ30 Plasma...
  • Page 69 0.43V 4) 5V VF 1.94V 0.43V Floating Gnd 3) Ground (F) Floating Gnd 2) Ground (F) Floating Gnd 1) Ground (F) P109 P209 Meter in the Diode Mode Y-SUS Board should be disconnected for this test. November 2009 50PQ30 Plasma...
  • Page 70 Y-SUS board is Look carefully. See Tip section supplied to the Lower page 133-134. Y-Drive Board on connector P205 pins 11 and 12. Then the Lower Y-Drive delivers the V-Scan signal to the upper via P209 to P108. November 2009 50PQ30 Plasma...
  • Page 71 P207 Pins 2, 3, 4, and 5 are 4) OC1 Logic (Drive) Signals to the 3) DATA Y-Drive lower P209 carries the P205 P207 2) OC2 Y-Drive signals to the Upper 1) Ground (F) Y-SUS Board Y-Drive Board Y-Drive board Bottom Connector P205 November 2009 50PQ30 Plasma...
  • Page 72 5) STB Open 0.538V 4) OC1 Open 0.538V 3) DATA Open Open 2) OC2 Open 0.521V P205 P207 Floating Gnd 1) Ground (F) Open Y-SUS Board should be disconnected for this test. Meter in the Diode Mode November 2009 50PQ30 Plasma...
  • Page 73 Y Scan *134V Open 1.0V Y Scan *134V Open 1.0V Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Y Scan *134V Open 1.0V Mode. Note: This voltage will vary in accordance with Panel Label November 2009 50PQ30 Plasma...
  • Page 74 To reinstall the Ribbon Cable, carefully slide it back into the slot see ( Fig 3 ), be sure the Tab is seated securely and press the Locking Tab back to the locked position see ( Fig 2 then Fig 1). November 2009 50PQ30 Plasma...
  • Page 75 Note the cable is crooked. In this case the Tab on the Ribbon cable was improperly seated at the top. This can cause bars, lines, intermittent lines abnormalities in the picture. Remove the ribbon cable and re-seat it correctly. November 2009 50PQ30 Plasma...
  • Page 76 128 Output Pins per/FPC (Flexible Printed Circuit) • Any of these output lugs can be tested. 6 Ribbon cables (Horizontal Electrodes) • Look for shorts indicating a defective Buffer IC 768 Total Horizontal Electrodes controlling Vertical resolution November 2009 50PQ30 Plasma...
  • Page 77 • DC Voltage and Waveform Test Points Locations • Z BIAS Alignment • Diode Mode Test Points Operating Voltages Operating Voltages Power Supply Supplied Control Board Supplied But developed on the Y-SUS Developed on Z-SUS Z Bias November 2009 50PQ30 Plasma...
  • Page 78 M5V from Y-SUS and 17V from the Control board Circuits generate erase, Generates Z Bias 100V sustain waveforms Via 3 FPC Flexible NO IPMs Printed Circuits FET Makes Drive waveform Display Simplified Block Diagram of Z-SUStain Board Panel Z-SUB November 2009 50PQ30 Plasma...
  • Page 79 No IPMs No IPMs Z-SUS Z-SUS Output Waveform Development Z-SUS Waveform Test Point Logic Signals from the Control board Also +15V generated on the Y-SUS and routed through the Control board. P105 To Z-SUB P100 P103 November 2009 50PQ30 Plasma...
  • Page 80 (Vzb) Z Bias VR200 J27 to check Z Output waveform. Right Hand side Center. Vzb voltage + - 1V 80 V 50V/div 400uS/div This Waveform is just for reference to observe the effects of Zbz adjustment November 2009 50PQ30 Plasma...
  • Page 81 Set should run for 15 minutes, this is the “Heat Run” mode. Set screen to “White Wash” mode or 100 IRE White input. Measured from Chassis Ground Adjust VZ (Z-Bias) to Panel Label (± 1V) November 2009 50PQ30 Plasma...
  • Page 82 11, 12 *193V Open Pin 1 * Note: This voltage will vary in accordance with Panel Label There are no Stand-By voltages on this connector Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. November 2009 50PQ30 Plasma...
  • Page 83 Z-SUS UP 0.2V Open Z-SUS DN 0.8V Open +15V Open Location: Bottom Left hand side +15V Open There are no Stand-By voltages on this connector Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. November 2009 50PQ30 Plasma...
  • Page 84 Reverse: Open Reverse: Open Q312 Blk Red Blk Red RF2001 Shown: Short Shown: 0.36V Shown: 0.36V D301 D305 D302 D306 Reverse: Short Reverse: Open Reverse: Open D303 D311 D304 D312 0.1 Ohms Blk Red Blk Red November 2009 50PQ30 Plasma...
  • Page 85 Reverse: 1.14V 0.49V Q315 Q302 Reverse: 0.782V Q317 0.95V Q304 Q318 Reverse: Open Q313 Q314 Blk Red Blk Red Shown: 1.22V Shown: 0.536V Shown: Open 5N50C Q321 Reverse: Open Reverse: Open Reverse: Open Blk Red Blk Red November 2009 50PQ30 Plasma...
  • Page 86 5V to any 5V location All this assumes the Power supply and Control board are working correctly. When you apply AC to the SMPS, check the Z-Bias waveform TP for 100V P/P Leave P101 to signal P100 Connected November 2009 50PQ30 Plasma...
  • Page 87 X Board Drive Signals (RGB Address) Operating Voltages Operating Voltages Y-SUS Supplied +5V (M5V) Developed on the SMPS +17V (Routed to the Z-SUS) Developed on the Control Board +1.8V for internal use +3.3V for internal use +3.3V for the X-Boars (TCPs) November 2009 50PQ30 Plasma...
  • Page 88 3) 4.96V 4) 5.74V D201 AUTO GEN TEST Pin 1 IC241 5) 4.91V Temp LED PATTERN 6) Gnd 3.3V 7) Gnd P161 8) 4.95V P162 Part Number Label To X Drive Cent To X Drive Cent November 2009 50PQ30 Plasma...
  • Page 89 50PQ30 CONTROL BOARD (Troubleshooting Tips) 50PQ30 CONTROL BOARD (Troubleshooting Tips) Unplug all connectors. Jump 5V from SMPS (P813 pins 9~12) to pin 1 of IC211. Observe LED. If it blinks, most likely Control PWB is OK. FL111 and FL112 should be checked.
  • Page 90 If there is a picture of cycling colors and patters, the Y-SUS, Y-Drive, Z-SUS, Power Supply, Control board, X-Boards, TCPs and Panel are all OK. Use the same test for problem (2) above to tell if the No Video is caused by the Main board or failed LVDS cable. November 2009 50PQ30 Plasma...
  • Page 91 Osc. Check: 25Mhz 1.5V ~ 1.8V Check the output of the Oscillator (Crystal). The frequency of the sine wave is 25 MHZ. Missing this clock signal will halt operation of CONTROL the panel drive signals. BOARD CRYSTAL LOCATION November 2009 50PQ30 Plasma...
  • Page 92 Menu Button “on” and “off” with the Remote Control or Keypad. Loss of these Signals would confirm the failure is on the Main Board! Menu ON Menu Off Main board P1002 Example of Normal Signals measured at 200mv/cm at 5µs/cm. November 2009 50PQ30 Plasma...
  • Page 93 Resistor Array 16 bit words IC201 EEPROM DRAM PANEL 2 Buffer Outputs There are 16 total TCPs. per TCP 4096 Vertical Electrodes 128 Lines per Buffer 1365 Total Pixels (H) 256 Lines output Total To Center X-Board November 2009 50PQ30 Plasma...
  • Page 94 Removing the LVDS Cable from the Control Board The LVDS Cable has two “Interlocks” that must be disengaged to remove the LVDS Cable. To Disengage, press the two Locking Tabs Inward and pull the plug out. Press Press Inward Inward November 2009 50PQ30 Plasma...
  • Page 95 Even pins on the All the rest are delivering Y-SUS board. Y-SUS Waveform development and Y-Drive logic signals to the Y-SUS Board (Y-Drive logic signals are simply routed right through the Y-SUS to the Y-Drive boards). Even Pins Pins November 2009 50PQ30 Plasma...
  • Page 96 The pin numbers are Silkscreen Label: correct. Remember The pin numbers are correct. Odd pins on the left Remember Odd pins on the left and even pins are on and even pins are on the right. the right. November 2009 50PQ30 Plasma...
  • Page 97 Open YO_SYS_DN 2.6V Open SET_UP 3.12V Open Y_ER)_UP 0.14V Open Y_PASS_TOP 1.1V Open Y_SUS_UP 0.11V Open There are no Stand-By voltages on this connector Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. November 2009 50PQ30 Plasma...
  • Page 98 P101 CONNECTOR “Control Board" to “Z-SUS" P100 Label Diode Mode Z_ENABLE 0.05V Open Z_Bias 1.8V Open SLOPE_CTRL 1.7V Open ZO_ER_Up 0.3V Open ZO_ER_Dn 0.4V Open ZO_SUS_Up 0.2V Open ZO_SUS_Dn 0.8V Open Open Pin 1 at the bottom Open of the connector November 2009 50PQ30 Plasma...
  • Page 99 RGB drive drive signals and signals 3.3V 3.3V created by IC221 Note: In this set, both connectors go to the The rest of the pins are much too Center X-Board close together for a safe test. November 2009 50PQ30 Plasma...
  • Page 100 BUS) The X Drive Boards deliver the Color drive signals to the Vertical Grids via TCPs. The 50PQ30 has a Left, Center and a Right X-Drive board. The Center X-Board has 6 connectors to a TCPs. The Left and Right have 5 connections to TCPs.
  • Page 101 LEFT X BOARD TCP IC’s shown are part of the Ribbon Cable P212 P211 P231 P232 CENTER X BOARD TCP IC’s shown are part of the Ribbon Cable P331 RIGHT X BOARD TCP IC’s shown are part of the Ribbon Cable November 2009 50PQ30 Plasma...
  • Page 102 TCP ICs receive RGB 16 bit signal and deliver it to the PDP by connecting the PAD Electrode of the PANEL with the X Board. X Drive Board Y-SUS Board Logic Control Board Taped Carrier Package Heat Sink Back side of TCP Ribbon November 2009 50PQ30 Plasma...
  • Page 103 Forward biased 9,30,37,38,39,40,41 On any Va On 3.3V On any signal Reverse Leads Reads Open Reversed biased 4,5,6,7,44,45,46,47 32 or 33 15,16,18,19,21, 22,24,26,31,36 Look for any TCPs being discolored. Ribbon Damage. Cracks, folds Pinches, scratches, etc… November 2009 50PQ30 Plasma...
  • Page 104 TCP 3.3V B+ Check Warning: DO NOT attempt to run the set with the Heat Sink over the TCPs removed. IC221 5V 3.3V 0V 3.3V Checking IC221 for 3.3V use center pin. P232 3.3V in on Pins 1~5 November 2009 50PQ30 Plasma...
  • Page 105 Generate abnormal vertical bars c) Cause the entire area driven by the TCP to be “All White” d) Cause the entire area driven by the TCP to be “All Black” e) Cause a “Single Line” defect November 2009 50PQ30 Plasma...
  • Page 106 P122 CONNECTOR "X Drive Left" to “Y-SUS" P202 Label Diode Mode *60V Open *60V Open *60V Open * Note: This voltage will vary in accordance with Panel Label Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. November 2009 50PQ30 Plasma...
  • Page 107 Voltage and Diode Mode Measurements for these connectors are difficult to read. They are too close together for safe test. The pins are also protected by a layer of tape to prevent the tab from being released causing separation from the Cable and the connector. November 2009 50PQ30 Plasma...
  • Page 108 Operating Voltages 5V Stand-By 12V (Tuner B+) 16V (Audio B+) 5V (MST) 3.3V (VST) Developed 3.3V (MST) 3.3V (DVDD) on the Main 3.3V (PVSB) 2.5V Board 1.8V (MST) 1.2V (VDDC) 1.2V (PVSB) 9V (TU) 5V (TU) November 2009 50PQ30 Plasma...
  • Page 109 12 Mhz Tuner IC504 X501 HDMI 3 25 Mhz IC1001 Pin 19 Audio RGB/DVI P1005 Optical Audio Tuner Component inputs Audio RS232 RGB/PC IC805 In 3 Pin 1 HDMI inputs A/V Composite inputs Wired Remote S-In November 2009 50PQ30 Plasma...
  • Page 110 50PQ30 MAIN PWB (Front Side) COMPONENT LAYOUT 50PQ30 MAIN PWB (Front Side) COMPONENT LAYOUT For component voltages, see the 50PQ30 Interconnect Section page 3. P1006 to SMPS P1003 LVDS IC302 IC203 IC804 P1001 USB Power IC503 Q301 L318 LVDS Driver 5V MST +1.2V_VDDC...
  • Page 111 50PQ30 MAIN PWB (Back Side) COMPONENT LAYOUT For component voltages, see the 50PQ30 Interconnect Section page 3. IC304 IC301 P1002 P1006 IC201 IC202 Q303 IC305 D1001 Q302 Q1001 Q504 IC502 Q502 Q891 IC601 Q501 Video 19 D802 SIF 16 IC803...
  • Page 112 Video Pin Video Test Point SIF Pin Audio Test Point Tuner B+ (5V) DIG IF (-) Pin DIG IF (+) Pin Digital Channel Test Point Data Pin Clock Pin MAIN Board Tuner Location Tuner B+ (5V) November 2009 50PQ30 Plasma...
  • Page 113 Signal 500mV / 10uSec Pin 16 “SIF” Signal 450mVp/p Pin 1 Pin 12 and Pin 13 “Dig IF” Signal 700mVp/p 200mV / 2uSec Note: “Dig IF” Signal only when 100mV / 1uSec receiving a Digital Channel. November 2009 50PQ30 Plasma...
  • Page 114 Main PWB Tuner Clock and Data Lines Main PWB Tuner Clock and Data Lines Note: Pin 8 SDA SCL and SDA only active during an actual Channel Change. 1V per/div 100uS 5V p/p Pin 9 SCL 1V per/div 100uS 5V p/p November 2009 50PQ30 Plasma...
  • Page 115 Left Side (1.576V DC) / (2.5V p/p) Right Side (1.6V DC) / (3V p/p) 12Mhz Runs all the time Top (1.49V DC)/(3.84V p/p) Bottom (1.58V DC)/(5.27V p/p) 25Mhz X501 MAIN Board Crystal Location Runs only on Digital Channels November 2009 50PQ30 Plasma...
  • Page 116 Pin 1 2uSec per/Div P1003 LVDS (Pin 11) 2uSec / 718mV P1003 LVDS (Pin 11) 5uSec / 642mV Pin 18 5uSec per/Div MAIN BOARD Pin 18 2uSec per/Div P1003 LVDS (Pin 11) 2uSec / 642mV 700mVp/p November 2009 50PQ30 Plasma...
  • Page 117 Open RL On 3.3V Open M5 ON 3.3V Open Auto Gnd Stby 5V 1.36V *Key On Open *Note: If the Key On line is 5V, the Main Power Switch is open. Stand-By 5V will shut off. November 2009 50PQ30 Plasma...
  • Page 118 This line is held low if the Main board has no power. Auto Gen on Control board will not work unless LVDS cable is removed. Diode Mode Readings with all Connectors Disconnected. DVM in the Diode mode. November 2009 50PQ30 Plasma...
  • Page 119 Open 0.961V * Pin 5 (Power Key) This pin is 0V when the button is lock “On” (In) and 5V when Locked “Off” (Out) Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. November 2009 50PQ30 Plasma...
  • Page 120 P1005 CONNECTOR "Main" to "Speakers" Label Diode Mode 8.65V Open Speakers 8.65V Open 8 Ohms 8.65V Open 8.65V Open P1005 Speaker Connector MAIN BOARD Diode Mode Readings with all Connectors Disconnected. DVM in the Diode mode. November 2009 50PQ30 Plasma...
  • Page 121 Unplug the connector P101. Ft IR Board Front Key Board Strap To left screw Screw Screw Master Power Switch Set will not function with this “Mechanical” switch down in the open position. “Disengaged” Button Assembly (Removed) Key Board P101 November 2009 50PQ30 Plasma...
  • Page 122 REMOVAL: Remove the 2 screws, pay attention to the Ground Strap on the left screw. Be sure to return this strap and IR problems may occur without it. Unplug the connectors J1 and J2. Front IR Board Strap Screw Screw With Gnd Strap J2 Pin November 2009 50PQ30 Plasma...
  • Page 123 The Ft Power LED board includes the IR Receiver and the Intelligent Sensor. The Front POWER LED is also located on this board. Front View IR Sensor INTELLIGENT FRONT POWER Sensor LEDs To Main Board Back View To Front Keys November 2009 50PQ30 Plasma...
  • Page 124 Place Voltmeter in Diode Mode, 0.653V 0.7V 0.687V Red on bottom of either LED black lead on top and they light. 0.652V 0.652V Leads opposite = Open Place Voltmeter in Diode Mode. Black on Gnd. Back View November 2009 50PQ30 Plasma...
  • Page 125 5VST 1.06V * Pin 5 (Power Key) 3.3VST 1.1V When this switch is out, Stand-By 5V turns off. LED-R 3.23V 3.22V LED-W 03.23 Open Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. November 2009 50PQ30 Plasma...
  • Page 126 * Use this in reference to pin for all Chassis Ground. readings. *STBY2 Main Power * Use this Switch “IN” Normal pin for Diode Mode readings. Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. November 2009 50PQ30 Plasma...
  • Page 127 SIDE KEY BOARD SECTION Side Key Board Layout (Component Identification) Side Key Board Layout (Component Identification) To Ft IR J2 P101 SW101 SW102 SW106 SW103 SW108 SW105 SW104 SW107 Main Power Button In (On) Out (Off) November 2009 50PQ30 Plasma...
  • Page 128 Side Key Board Layout P101 The Ft Key board contains the Master Power Switch, Volume Up/Down and Channel Up/Down keys. Also the Menu and Select keys. To Front LED Board Rear View P101 Main Power Switch Front View P101 November 2009 50PQ30 Plasma...
  • Page 129 * This pin is open Main Power *Open in reference to Switch Out Chassis Ground. PWR SW 4.38V Open STBY 2 * Use this KEY 2 3.3V Open Main Power pin for all KEY 1 3.3V Open Switch In readings. November 2009 50PQ30 Plasma...
  • Page 130 Diode Mode Readings taken with all connectors Cushion Cushion Disconnected. DVM in Diode Mode. Speaker At the top of the speaker is a rubber cushion. Be sure to return this to its proper position to prevent vibrations. November 2009 50PQ30 Plasma...
  • Page 131 50PQ30 SERVICE TIP SECTION 50PQ30 SERVICE TIP SECTION Floating Ground checks must be made from Floating Ground. Use any pin on P204, P203, P205 or P208. TIP: SYMPTOM: The panel indicates a brief flash during start up, then “No Picture” symptom.
  • Page 132 It was stuck. FIX: 1. Removing and repositioning the button assembly freed up the button. The set return to normal function. (See page 116 for more details). November 2009 50PQ30 Plasma...
  • Page 133 Jump either Pin 1 or 2 of P207 (V-Scan from the Y-SUS) to pin 4 or 5 of connector P108 on the Upper Y-Drive board. • Turn on the set and confirm that the top half of the picture looks normal. November 2009 50PQ30 Plasma...
  • Page 134 Improperly Seated Properly Seated Connector Connector Note the pins are Note now the pins are visible across the not visible across the top inside of the top inside of the connector. connector. November 2009 50PQ30 Plasma...
  • Page 135 50PQ30 INTERCONNECT DIAGRAM SECTION 50PQ30 INTERCONNECT DIAGRAM SECTION 11 X 17 Foldout Section 11 X 17 Foldout Section This section shows the 11X17 foldout that ’ s available in the Adobe This section shows the 11X17 foldout that ’ s available in the Adobe version of the Training Manual.
  • Page 136 50PQ30 (50G2 Panel) CIRCUIT INTERCONNECT DIAGRAM 50PQ30 (50G2 Panel) CIRCUIT INTERCONNECT DIAGRAM NOTE: Diode tests are conducted with the PWB disconnected. Y-DRIVE WAVEFORM VS to Z-SUS and Error Com from the Z-SUS VR601 Z-SUS SMPS Test – Unplug P813, ground pin 24.
  • Page 137 50PQ30 LVDS P1003 LVDS (Pin 11) 5uSec / 718mV P1003 LVDS (Pin 12) 5uSec / 565mV P1003 LVDS (Pin 13) 5uSec / 479mV P1003 LVDS (Pin 14) 5uSec / 594mV P1003 WAVEFORMS Connector P1003 Configuration indicates signal pins. P1003 LVDS (Pin 11) 2uSec / 718mV...
  • Page 138 50PQ30 MAIN (BACK SIDE) SIMICONDUCTORS IC201 NVRAM IC304 1.8VMST IC505 5V (Tuner) IC602 RS232 RAM Q1001 Pow Down Q502 Video Buffer Q890/2 HDMI1/2 IC1001 Pin Hot Swap [1] Gnd [1] 0.6V [1] 3.8V [1] Gnd [B] 0V [B] 0.6V [B] 0V [2] Gnd [2] 1.85V...
  • Page 139: Thank You

    End of Presentation End of Presentation This concludes the Presentation Thank You Preliminary Information 50PQ30...