Pioneer CDJ-800MK2 Service Manual page 40

1
A
A
MAIN ASSY
MPU
Delay time of Reset IC (IC304)
CH1 : V+3D
22
V: 2.0 V/div. H: 10 msec/div.
CH2 : RST from Reset IC to CPU
18
V: 2.0 V/div. H: 10 msec/div.
Conditions: At the time of power on, without a disc loaded
Remark: Set value for reset delay time: 70 msec
B
CH1
Power ON
CH2
a
MPU
Association between the 16.93 MHz clock
signal and resetting of the MPU
C
CH1 : V+3D
22
V: 5.0 V/div. H: 10 msec/div.
CH2 : CPU16M from IC310 to CPU
71
V: 5.0 V/div. H: 10 msec/div.
CH3 : RST from Reset IC to CPU
18
V: 5.0 V/div. H: 10 msec/div.
Conditions: At the time of power on, without a disc loaded
CH1
CH2
D
CH3
a
FPGA
Configuration (1/3)
CH1 : PROG_B (IC302 - pin 99) from CPU to FPGA
23
V: 5.0 V/div. H: 100 msec/div.
CH2 : XINIT to CPU
24
V: 5.0 V/div. H: 100 msec/div.
CH3 : CLK from CPU to FPGA
25
V: 5.0 V/div. H: 100 msec/div.
CH4 : DATA from CPU
E
26
V: 5.0 V/div. H: 100 msec/div.
Conditions: At the time of power on, without a disc loaded
CH1
a
CH2
CH3
F
CH4 b
40
1
2
FPGA
Configuration (2/3)
CH2 : XINIT to CPU
24
V: 5.0 V/div. H: 100 msec/div.
CH4 : DATA from CPU
26
V: 5.0 V/div. H: 100 msec/div.
CH5 : DONE to CPU
27
V: 5.0 V/div. H: 100 msec/div.
CH8 : XFRST from CPU
30
V: 5.0 V/div. H: 100 msec/div.
Conditions: At the time of power on, without a disc loaded
a - b : 68.7 msec
CH2
a
3.3 V
CH4
Reset clear
CH5
3.3 V
b
CH8
FPGA
Configuration (3/3)
CH5 : DONE to CPU
27
V: 5.0 V/div. H: 100 msec/div.
CH6 : SRV16M to IC101
28
V: 5.0 V/div. H: 100 msec/div.
CH7 : DSP16M to IC701
29
V: 5.0 V/div. H: 100 msec/div.
CH8 : XFRST from CPU
30
V: 5.0 V/div. H: 100 msec/div.
Conditions: At the time of power on, without a disc loaded
a - b : 67.8 msec
CH5
a
CH6
CH7
b
CH8
Audio DSP
Configuration (1/2)
CH1 : DSP16M from FPGA
29
V: 5.0 V/div. H: 200 msec/div.
CH2 : DSPRST from CPU
21
V: 5.0 V/div. H: 200 msec/div.
CH3 : DSPSIN to CPU
31
V: 5.0 V/div. H: 200 msec/div.
CH4 : CLK from CPU
32
V: 5.0 V/div. H: 200 msec/div.
Conditions: At the time of power on, without a disc loaded
a - b : 69 msec
a - c : 442 msec
b - c : 373 msec
CH1
c
a
CH2
CH3
CH4
CDJ-800MK2
2
3
Audio DSP
Configuration (2/2)
CH1 : DSP16M from FPGA
29
V: 5.0 V/div. H: 200 msec/div.
CH5 : DATA from CPU
26
V: 5.0 V/div. H: 200 msec/div.
CH6 : DSPDREQ to FPGA & CPU
34
V: 5.0 V/div. H: 200 msec/div.
CH7 : DAC11M to IC702
35
V: 5.0 V/div. H: 200 msec/div.
Conditions: At the time of power on, without a disc loaded
a - b : 442 msec
a - c : 682 msec
CH1
b
CH5
c
CH6
CH7
Servo DSP
Configuration (1/2)
CH1 : SRV16M from FPGA
28
V: 5.0 V/div. H: 200 msec/div.
CH2 : SRVRST from CPU
20
V: 5.0 V/div. H: 200 msec/div.
CH3 : SRVBUS0 CPU - SRV
36
V: 5.0 V/div. H: 200 msec/div.
CH4 : DRVMUTE1 from CPU to IC102
37
V: 5.0 V/div. H: 200 msec/div.
Conditions: At the time of power on, without a disc loaded
a - b : 681 msec
CH1
b
CH2
CH3
CH4
Servo DSP
Configuration (2/2)
CH1 : SRV16M from FPGA
28
V: 5.0 V/div. H: 200 msec/div.
CH2 : SRVRST from CPU
20
V: 5.0 V/div. H: 200 msec/div.
CH3 : SRVBUS0 CPU - SRV
36
V: 5.0 V/div. H: 200 msec/div.
CH5 : DRVMUTE2 from CPU to IC102
38
V: 5.0 V/div. H: 200 msec/div.
Conditions: At the time of power on, without a disc loaded
a - b : 680 msec
b
CH1
CH2
CH3
CH5
3
4
a - b : 670 msec
a b
a - b : 1 256 msec
a
b
a - b : 1 256 msec
a - c : 1 318 msec
a
b
c
4