Pioneer CDJ-800MK2 Service Manual page 125

5
PEG237B (DFLB ASSY : IC501)
• Display Microcomputer
Pin Arrangement (Top view)
P0_7/AN0_7 81
P0_6/AN0_6 82
83
P0_5/AN0_5
P0_49AN0_4 84
P0_3/AN0_3 85
P0_2/AN0_2 86
P0_1/AN0_1 87
P0_0/AN0_0 88
P10_7/AN7/KI3 89
P10_6/AN6/KI2 90
P10_5/AN5/KI1 91
P10_4/AN4/KI0 92
93
P10_3/AN3
P10_2/AN2 94
P10_1/AN1 95
AVSS 96
P10_0/AN0
97
VREF 98
AVCC 99
P9_7/ADTRG
100
Block Diagram
8
Port P0
Internal peripheral functions
Timer (16-bit)
Output (timer A): 3
Input (timer B): 3
Watchdog timer
(15 bits)
DMAC
(2 channels)
5
6
M16C/30P Group
8 8 8
Port P1 Port P2 Port P3
A/D converter
(10 bits x 18 channels)
UART or
clock synchronous serial I/O
(3 channels)
CRC arithmetic circuit (CCITT)
16
(Polynomial : X
M16C/60 series16-bit CPU core
R0H R0L
R1H
R1L
R2
R3
A0
A1
FB
CDJ-800MK2
6
7
8 8 8
Port P4 Port P5 Port P6
System clock
generation circuit
XIN-XOUT
XCIN-XCOUT
12 5
+X +X +1)
Memory
ROM
SB
(Note 1)
USP
ISP
RAM
INTB (Note 2)
PC
FLG
Multiplier
(Note 1) ROM size depends on microcomputer type.
(Note 2) RAM size depends on microcomputer type.
7
8
50 P4_4
49 P4_5
48
P4_6
47 P4_7
46 P5_0
45 P5_1
44 P5_2
43 P5_3
42 P5_4
41 P5_5
40 P5_6
39 P5_7/CLKOUT
38
P6_0/CTSWRTS0
37 P6_1/CLK0
36 P6_2/RXD0/SCL0
35 P6_3/TXD0/SDA0
P6_4/CST1/RTS1/CTS0/CLKS1
34
33 P6_5/CLK1
32 P6_6/RXD1/SCL1
31 P6_7/TXD1/SDA1
NOTES:
1. P7_0 and P7_1 are N channel open-drain
output pins.
2. Use the M16C/30P on VCC1=VCC2.
8
A
B
C
D
E
F
125